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authorRizwan Qureshi <rizwan.qureshi@intel.com>2015-10-15 21:38:21 +0530
committerPatrick Georgi <pgeorgi@google.com>2015-11-05 17:39:46 +0100
commit0dd72e8b1db78558ef148a5d67a2d12e73c36b94 (patch)
tree14dd0ad5e3ed5fb352dffe470738e0274c88a855 /src/soc/intel/skylake/cpu.c
parentf86d0351051bddf98ed96a5da044b9779e35e9a1 (diff)
downloadcoreboot-0dd72e8b1db78558ef148a5d67a2d12e73c36b94.tar.xz
skylake: Set Pkg Power clamping bit in Power Limit MSR
Setting the Package Power clamping bits in Power Limit MSR (MSR_PKG_POWER_LIMIT 0x610) Allows going below the OS requested P or T state for the time window specified for PL1 or PL2. BRANCH=none BUG=chrome-os-partner:47041 TEST=Built and boot on kunimitsu, load the system with Aquarium WebGL, change the power limit value from default (TDP or 15W) to any lower value note that the Pkg power comes down and also the CPU frequency is lowered. Change-Id: I9c0dd90a6660214ae142418aae8b8c5f6a739896 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b0b527991c2d26da5772700a22ff101eaf9993ef Original-Change-Id: Ia59fcfe2a14cd7f8b1e1b8e967073e67eb452f42 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309556 Original-Tested-by: Charulatha Varadarajan <charuprasanna@gmail.com> Original-Tested-by: Charulatha Varadarajan <charulatha.varadarajan@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12257 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/cpu.c')
-rw-r--r--src/soc/intel/skylake/cpu.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index a5c60b81f2..368738057f 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -152,6 +152,10 @@ void set_power_limits(u8 power_limit_1_time)
/* Set long term power limit to TDP */
limit.lo = 0;
limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+
+ /* Set PL1 Pkg Power clamp bit */
+ limit.lo |= PKG_POWER_LIMIT_CLAMP;
+
limit.lo |= PKG_POWER_LIMIT_EN;
limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
PKG_POWER_LIMIT_TIME_SHIFT;
@@ -159,6 +163,7 @@ void set_power_limits(u8 power_limit_1_time)
/* Set short term power limit to 1.25 * TDP */
limit.hi = 0;
limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+ limit.hi |= PKG_POWER_LIMIT_CLAMP;
limit.hi |= PKG_POWER_LIMIT_EN;
/* Power limit 2 time is only programmable on server SKU */