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| author | Subrata Banik <subrata.banik@intel.com> | 2017-05-12 11:43:57 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-05-16 17:45:38 +0200 |
| commit | 6b45ee44a9bbccb4dc42ea454aa20ef7d02a9fd1 (patch) | |
| tree | ef5eb4fa57c2bde345e5cec61668e33fe1d311b3 /src/soc/intel/skylake/cpu.c | |
| parent | 481b364222322b96dc16ebc126040ed9c0aa2811 (diff) | |
| download | coreboot-6b45ee44a9bbccb4dc42ea454aa20ef7d02a9fd1.tar.xz | |
soc/intel/skylake: Add option to enable/disable EIST
Set MSR 0x1A0 bit[16] based on EIST config option.
Default Hardware Managed P-state (HWP) also known as Intel Speed Shift
is enabled on SKL hence disable EIST and ACPI P-state table.
Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/skylake/cpu.c')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index c472617b0f..057241327b 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -245,12 +245,17 @@ static void configure_isst(void) static void configure_misc(void) { + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + if (conf->eist_enable) + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + else + msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ |