diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2017-06-12 23:02:36 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-10 17:16:26 +0000 |
| commit | a04aa3d5662149b70f31e0e6584bd8c6087b5f3b (patch) | |
| tree | 9886be703d858b08525743fe0bdcf2b921d9b07f /src/soc/intel/skylake/cpu.c | |
| parent | 8c94e14a0c0e77061d8fb879f4bf7bc1347b38d2 (diff) | |
| download | coreboot-a04aa3d5662149b70f31e0e6584bd8c6087b5f3b.tar.xz | |
sgx: Move SGX code to intel/common/block
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX controls building. The SGX feature
is still enabled from devicetree.cb. As of now this SGX init supports
only KBL (SKL not tested). Support of SGX for new SOCs would be added
incrementally in this common code base.
Change-Id: I0fbba364b7342e686a2287ea1a910ef9a4eed595
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/cpu.c')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index e3be73870f..7f455e0d59 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -37,6 +37,7 @@ #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <intelblocks/mp_init.h> +#include <intelblocks/sgx.h> #include <pc80/mc146818rtc.h> #include <soc/cpu.h> #include <soc/msr.h> @@ -422,7 +423,7 @@ void soc_core_init(device_t cpu, const void *microcode) enable_turbo(); /* Configure SGX */ - configure_sgx(microcode); + sgx_configure(microcode); } static int adjust_apic_id(int index, int apic_id) @@ -489,7 +490,7 @@ void soc_init_cpus(struct bus *cpu_bus, const void *microcode) * here to get SGX enabled on BSP. This behavior needs to root-caused * and we shall not have this redundant call. */ - configure_sgx(microcode); + sgx_configure(microcode); } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) @@ -514,3 +515,14 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) return (msr1.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); } + +void cpu_lock_sgx_memory(void) +{ + msr_t msr; + + msr = rdmsr(MSR_LT_LOCK_MEMORY); + if ((msr.lo & 1) == 0) { + msr.lo |= 1; /* Lock it */ + wrmsr(MSR_LT_LOCK_MEMORY, msr); + } +} |