diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2015-07-23 22:40:53 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-29 20:26:35 +0200 |
| commit | a7ff45309020118cb88fae98ffe9da5c856f83e2 (patch) | |
| tree | 7462e44abcae0aff482f3d04e9d45536335498ff /src/soc/intel/skylake/cpu.c | |
| parent | 30b755be2b798c228745661393efd8f2fe42e6d8 (diff) | |
| download | coreboot-a7ff45309020118cb88fae98ffe9da5c856f83e2.tar.xz | |
skylake: Update microcode reload in ramstage.
For Skylake, Microcode is being loaded from FIT, Skylake supports
the PRMRR/SGX feature. If This is supported the FIT microcode
load will set the msr (0x08b) with the Patch id one less than the
id in the microcode binary. This results in Microcode getting
reloaded again in bootclock and ramstage (MP init).
Avoid the microcode reload by checking for PRMRR support.
BUG=chrome-os-partner:42046
BRANCH=None TEST=Built for glados and tested on RVP3
CQ-DEPEND=CL:287513
Change-Id: Ic5dbf4d14dc1441e5b5acead589a418687df7dca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c599714b2aef476297eeaad5da8975731b12785a
Original-Change-Id: Id3a387aa2d8fd2fd69052bfc7b4e88a7ec277a72
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/287674
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11056
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/skylake/cpu.c')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index cd88c10e76..980a05a577 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -574,3 +574,16 @@ void soc_init_cpus(device_t dev) if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) restore_default_smm_area(smm_save_area); } + +int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) +{ + msr_t msr; + /* If PRMRR/SGX is supported the FIT microcode load will set the msr + * 0x08b with the Patch revision id one less than the id in the + * microcode binary. The PRMRR support is indicated in the MSR + * MTRRCAP[12]. Check for this feature and avoid reloading the + * same microcode during cpu initialization. + */ + msr = rdmsr(MTRRcap_MSR); + return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); +} |