diff options
| author | Archana Patni <archana.patni@intel.com> | 2015-11-11 01:29:23 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-17 22:54:17 +0100 |
| commit | 7846e34c02473a2a000e1fda1e2051475ef3fbf1 (patch) | |
| tree | dba3417a968fa94dd241cbcd85be65eb5975b9fb /src/soc/intel/skylake/finalize.c | |
| parent | df13c31ed6fdad2cdb6e8e874f26e5cad2ce935f (diff) | |
| download | coreboot-7846e34c02473a2a000e1fda1e2051475ef3fbf1.tar.xz | |
intel/skylake: disable heci1 if psf is unlocked
This patch adds support for disabling the heci1 device
at the end of boot sequence. Prior to this, FSP would have
sent the end of post message to ME and initiated the d0i3 bit.
This uses the Psf unlock policy and the p2sb device to disable
the heci1 device, then lock the configuration and hide the device.
BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu or glados board. set the hecienabled policy
to 0 and check for heci 1 device status in kernel lspci.
CQ-DEPEND=CL:*238451
Change-Id: I26b145231f8ed0c140af42d378b222e857d9aff6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fe184b8baf1bea9bcd0af1841785a4d763af9358
Original-Change-Id: I3b435491aeea0f2ca36b7877e942dc940560e4dd
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311912
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12976
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/finalize.c')
| -rw-r--r-- | src/soc/intel/skylake/finalize.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index e2577aadeb..8069b405e8 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -31,6 +31,55 @@ #include <soc/spi.h> #include <soc/systemagent.h> #include <device/pci.h> +#include <chip.h> + +#define PCH_P2SB_EPMASK0 0xB0 +#define PCH_P2SB_EPMASK(mask_number) PCH_P2SB_EPMASK0 + (mask_number * 4) + +#define PCH_P2SB_E0 0xE0 + +static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask) +{ + uint32_t reg32; + + reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id)); + pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); +} + +static void pch_disable_heci(void) +{ + device_t dev; + u8 reg8; + uint32_t mask; + + dev = PCH_DEV_P2SB; + + /* + * if p2sb device 1f.1 is not present or hidden in devicetree + * p2sb device becomes NULL + */ + if (!dev) + return; + + /* unhide p2sb device */ + pci_write_config8(dev, PCH_P2SB_E0 + 1, 0); + + /* disable heci */ + pcr_andthenor32(PID_PSF1, PSF_BASE_ADDRESS + PCH_PCR_PSFX_T0_SHDW_PCIEN, + ~0, PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); + + /* Remove the host accessing right to PSF register range. */ + /* Set p2sb PCI offset EPMASK5 C4h [29, 28, 27, 26] to [1, 1, 1, 1] */ + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); + pch_configure_endpoints(dev, 5, mask); + + /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ + reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2); + pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1)); + + /* hide p2sb device */ + pci_write_config8(dev, PCH_P2SB_E0 + 1, 1); +} static void pch_finalize_script(void) { @@ -40,6 +89,7 @@ static void pch_finalize_script(void) u16 tcobase; u16 tcocnt; uint8_t *pmcbase; + config_t *config; u32 pmsyncreg; /* Set SPI opcode menu */ @@ -69,6 +119,11 @@ static void pch_finalize_script(void) pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); pmsyncreg |= PMSYNC_LOCK; write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); + + /* we should disable Heci1 based on the devicetree policy */ + config = dev->chip_info; + if (config->HeciEnabled == 0) + pch_disable_heci(); } static void soc_lockdown(void) |