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authorSubrata Banik <subrata.banik@intel.com>2017-08-14 16:15:33 +0530
committerAaron Durbin <adurbin@chromium.org>2017-08-25 18:02:06 +0000
commitb51f54b518bf17a1bfb678d3d14dcf0996d882d2 (patch)
tree1e016479f41745936f40edbfe11d4a6d1405b1d5 /src/soc/intel/skylake/finalize.c
parent2d1dd5943d12a6ef46ab6d3d580545e89622e47d (diff)
downloadcoreboot-b51f54b518bf17a1bfb678d3d14dcf0996d882d2.tar.xz
soc/intel/skylake: Move LPC lock down config after resource allocation
This patch to ensures that coreboot is performing LPC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence lpc register lock down has been moved right after pci resource allocation is done, so that lpc registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure LPC register 0xDC bit 1 and 7 is set. Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/finalize.c')
-rw-r--r--src/soc/intel/skylake/finalize.c13
1 files changed, 0 insertions, 13 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 404d217a87..a793e9551c 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -186,25 +186,12 @@ static void soc_lockdown(void)
if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
/* Bios Interface Lock */
- pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
- pci_read_config8(PCH_DEV_LPC,
- BIOS_CNTL) | LPC_BC_BILD);
- /* Reads back for posted write to take effect */
- pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
-
fast_spi_set_bios_interface_lock_down();
/* GCS reg of DMI */
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
/* Bios Lock */
- pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
- pci_read_config8(PCH_DEV_LPC,
- BIOS_CNTL) | LPC_BC_LE);
-
- /* Ensure an additional read back after performing lock down */
- pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
-
fast_spi_set_lock_enable();
}
}