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authorRizwan Qureshi <rizwan.qureshi@intel.com>2016-08-04 20:01:12 +0530
committerMartin Roth <martinroth@google.com>2016-08-18 06:26:40 +0200
commitcf73c1317dd1ab62a96eb17ed6d9c8590fb4c514 (patch)
treee8b463fb1fed894b6d432b37028c549bf5829202 /src/soc/intel/skylake/finalize.c
parent4a36c4e9fc66bf442f46e1e6d742b2d6c50a2ae1 (diff)
downloadcoreboot-cf73c1317dd1ab62a96eb17ed6d9c8590fb4c514.tar.xz
skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init
Prepare Skylake for FSP2.0 support. We do not use FSP-T in FSP2.0 driver, hence guard the FspTempRamInit call under a switch. In addition to the current early PCH configuration program few more register, so all in all we do the following, * Program and enable ACPI Base. * Program and enable PWRM Base. * Program TCO Base. * Program Interrupt configuration registers. * Program LPC IO decode range. * Program SMBUS Base address and enable it. * Enable upper 128 bytes of CMOS. And split the above programming into into smaller functions. Also, as part of bootblock_pch_early_init we enable decoding for HPET range. This is needed for FspMemoryInit to store and retrieve a global data pointer. And also move P2SB related definitions to a new header file. TEST=Build and boot Kunimitsu Change-Id: Ia201e03b745836ebb43b8d7cfc77550105c71d16 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16113 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/finalize.c')
-rw-r--r--src/soc/intel/skylake/finalize.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index e5b92c6966..e923dcdf24 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -25,6 +25,7 @@
#include <stdlib.h>
#include <soc/lpc.h>
#include <soc/me.h>
+#include <soc/p2sb.h>
#include <soc/pci_devs.h>
#include <soc/pcr.h>
#include <soc/pm.h>
@@ -34,12 +35,6 @@
#include <device/pci.h>
#include <chip.h>
-#define PCH_P2SB_EPMASK0 0xB0
-#define PCH_P2SB_EPMASK(mask_number) PCH_P2SB_EPMASK0 + (mask_number * 4)
-
-#define PCH_P2SB_E0 0xE0
-#define PCH_PWRM_ACPI_TMR_CTL 0xFC
-
static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
{
uint32_t reg32;