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authorShelley Chen <shchen@chromium.org>2017-06-29 11:31:16 -0700
committerAaron Durbin <adurbin@chromium.org>2017-07-14 22:47:25 +0000
commit20c3ea5c4f2c83df7c9416b2b9cbcff63e2c74f1 (patch)
tree4f53314fef60d9a75fea39ce13e76bd85e3f9c5b /src/soc/intel/skylake/include
parent2a7fbea3f14cae2119816c5a28c455f45c75650f (diff)
downloadcoreboot-20c3ea5c4f2c83df7c9416b2b9cbcff63e2c74f1.tar.xz
soc/intel/skylake: Set PsysPL2 MSR
BUG=b:7473486, b:35775024 BRANCH=None TEST=On bootup make sure PL2 and PsysPL2 values set properly (through debug output) Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/soc/msr.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index 81b6cc9de1..4ff4ad2d49 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -37,5 +37,6 @@
#define MSR_VR_MISC_CONFIG2 0x636
#define MSR_PP0_POWER_LIMIT 0x638
#define MSR_PP1_POWER_LIMIT 0x640
+#define MSR_PLATFORM_POWER_LIMIT 0x65c
#endif