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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-03-31 18:11:49 +0530
committerFurquan Shaikh <furquan@google.com>2017-05-02 18:26:07 +0200
commit7146445be9618eb47895782912af28fb627c009d (patch)
treeec95cd0ab17fecd4ce91bb9b6bff459d9459f3f4 /src/soc/intel/skylake/include
parentc261c4b426ac806cca732bb30459f0e6e855828a (diff)
downloadcoreboot-7146445be9618eb47895782912af28fb627c009d.tar.xz
soc/intel/skylake: Clean up code by using common FAST_SPI module
This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19055 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/fsp11/soc/romstage.h1
-rw-r--r--src/soc/intel/skylake/include/fsp20/soc/romstage.h1
-rw-r--r--src/soc/intel/skylake/include/soc/flash_controller.h181
-rw-r--r--src/soc/intel/skylake/include/soc/pch.h1
-rw-r--r--src/soc/intel/skylake/include/soc/spi.h126
5 files changed, 0 insertions, 310 deletions
diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
index f3e4371352..36825f7aea 100644
--- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
@@ -24,7 +24,6 @@ void intel_early_me_status(void);
void enable_smbus(void);
int smbus_read_byte(unsigned int device, unsigned int address);
-int early_spi_read_wpsr(u8 *sr);
void mainboard_fill_spd_data(struct pei_data *pei_data);
#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
index 6bdc3b5858..cdcc8fbc28 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
@@ -23,7 +23,6 @@
void mainboard_memory_init_params(FSPM_UPD *mupd);
void systemagent_early_init(void);
int smbus_read_byte(unsigned int device, unsigned int address);
-int early_spi_read_wpsr(u8 *sr);
/* Board type */
enum board_type {
BOARD_TYPE_MOBILE = 0,
diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h
deleted file mode 100644
index 712a18df19..0000000000
--- a/src/soc/intel/skylake/include/soc/flash_controller.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_FLASH_CONTROLLER__H_
-#define _SOC_FLASH_CONTROLLER__H_
-
-#include <rules.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <spi_flash.h>
-
-int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len);
-int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
- const void *buf);
-int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
- void *buf);
-int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg);
-
-void spi_flash_init(void);
-
-#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
-static u8 readb_(const void *addr)
-{
- u8 v = read8(addr);
- printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
- v, ((unsigned int) addr & 0xffff) - 0xf020);
- return v;
-}
-
-static u16 readw_(const void *addr)
-{
- u16 v = read16(addr);
- printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
- v, ((unsigned int) addr & 0xffff) - 0xf020);
- return v;
-}
-
-static u32 readl_(const void *addr)
-{
- u32 v = read32(addr);
- printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
- v, ((unsigned int) addr & 0xffff) - 0xf020);
- return v;
-}
-
-static void writeb_(u8 b, void *addr)
-{
- write8(addr, b);
- printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
- b, ((unsigned int) addr & 0xffff) - 0xf020);
-}
-
-static void writew_(u16 b, void *addr)
-{
- write16(addr, b);
- printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
- b, ((unsigned int) addr & 0xffff) - 0xf020);
-}
-
-static void writel_(u32 b, void *addr)
-{
- write32(addr, b);
- printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
- b, ((unsigned int) addr & 0xffff) - 0xf020);
-}
-
-#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-
-#define readb_(a) read8(a)
-#define readw_(a) read16(a)
-#define readl_(a) read32(a)
-#define writeb_(val, addr) write8(addr, val)
-#define writew_(val, addr) write16(addr, val)
-#define writel_(val, addr) write32(addr, val)
-
-#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
-
-#if ENV_SMM
-#define pci_read_config_byte(dev, reg, targ)\
- (*(targ) = pci_read_config8(dev, reg))
-#define pci_read_config_word(dev, reg, targ)\
- (*(targ) = pci_read_config16(dev, reg))
-#define pci_read_config_dword(dev, reg, targ)\
- (*(targ) = pci_read_config32(dev, reg))
-#define pci_write_config_byte(dev, reg, val)\
- pci_write_config8(dev, reg, val)
-#define pci_write_config_word(dev, reg, val)\
- pci_write_config16(dev, reg, val)
-#define pci_write_config_dword(dev, reg, val)\
- pci_write_config32(dev, reg, val)
-#else /* !ENV_SMM */
-#include <device/device.h>
-#include <device/pci.h>
-#define pci_read_config_byte(dev, reg, targ)\
- (*(targ) = pci_read_config8(dev, reg))
-#define pci_read_config_word(dev, reg, targ)\
- (*(targ) = pci_read_config16(dev, reg))
-#define pci_read_config_dword(dev, reg, targ)\
- (*(targ) = pci_read_config32(dev, reg))
-#define pci_write_config_byte(dev, reg, val)\
- pci_write_config8(dev, reg, val)
-#define pci_write_config_word(dev, reg, val)\
- pci_write_config16(dev, reg, val)
-#define pci_write_config_dword(dev, reg, val)\
- pci_write_config32(dev, reg, val)
-#endif /* ENV_SMM */
-
-#define HSFC_FCYCLE_MASK (0xf << HSFC_FCYCLE_SHIFT)
-#define HSFC_FCYCLE_RD (0x0 << HSFC_FCYCLE_SHIFT)
-#define HSFC_FCYCLE_WR (0x2 << HSFC_FCYCLE_SHIFT)
-#define HSFC_FCYCLE_4KE (0x3 << HSFC_FCYCLE_SHIFT)
-#define HSFC_FCYCLE_64KE (0x4 << HSFC_FCYCLE_SHIFT)
-#define HSFC_FCYCLE_SFDP (0x5 << HSFC_FCYCLE_SHIFT)
-#define HSFC_FCYCLE_JEDECID (0x6 << HSFC_FCYCLE_SHIFT)
-#define HSFC_FCYCLE_WS (0x7 << HSFC_FCYCLE_SHIFT)
-#define HSFC_FCYCLE_RS (0x8 << HSFC_FCYCLE_SHIFT)
-#define HSFC_FDBC_MASK (0x3f << HSFC_FDBC_SHIFT)
-
-#define SPI_READ_STATUS_LENGTH 1 /* Read Status Register 1 */
-
-#define WPSR_MASK_SRP0_BIT 0x80
-
-#define SPI_FDATA_REGS 16
-#define SPI_FDATA_BYTES (SPI_FDATA_REGS * sizeof(uint32_t))
-
-typedef struct pch_spi_flash_regs {
- uint32_t bfpr;
- uint16_t hsfs;
- uint16_t hsfc;
- uint32_t faddr;
- uint32_t dlock;
- uint32_t fdata[SPI_FDATA_REGS];
- uint32_t frap;
- uint32_t freg[6];
- uint32_t _reserved1[6];
- uint32_t pr[5];
- uint32_t gpr0;
- uint32_t _reserved2;
- uint32_t _reserved3;
- uint16_t preop;
- uint16_t optype;
- uint8_t opmenu[8];
- uint32_t bbar;
- uint32_t fdoc;
- uint32_t fdod;
- uint8_t _reserved4[8];
- uint32_t afc;
- uint32_t lvscc;
- uint32_t uvscc;
- uint8_t _reserved5[4];
- uint32_t fpb;
- uint8_t _reserved6[28];
- uint32_t srdl;
- uint32_t srdc;
- uint32_t srd;
-} __attribute__((packed)) pch_spi_flash_regs;
-
-enum {
- HSFS_FDONE = 0x0001,
- HSFS_FCERR = 0x0002,
- HSFS_FDV = 0x4000,
-};
-
-enum {
- HSFC_FGO = 0x0001,
- HSFC_FCYCLE_SHIFT = 1,
- HSFC_FDBC_SHIFT = 8,
-};
-#endif /* _SOC_FLASH_CONTROLLER__H_ */
diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h
index d8e5b96491..9602f10d31 100644
--- a/src/soc/intel/skylake/include/soc/pch.h
+++ b/src/soc/intel/skylake/include/soc/pch.h
@@ -37,7 +37,6 @@
u8 pch_revision(void);
u16 pch_type(void);
-u32 pch_read_soft_strap(int id);
void pch_log_state(void);
#if ENV_RAMSTAGE
void pch_disable_devfn(device_t dev);
diff --git a/src/soc/intel/skylake/include/soc/spi.h b/src/soc/intel/skylake/include/soc/spi.h
deleted file mode 100644
index a92b78d0c9..0000000000
--- a/src/soc/intel/skylake/include/soc/spi.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_SPI_H_
-#define _SOC_SPI_H_
-
-/*
- * SPI Opcode Menu setup for SPIBAR lockdown
- * should support most common flash chips.
- */
-#define SPIDVID_OFFSET 0x0
-
-/* Reigsters within the SPIBAR */
-#define SPIBAR_SSFC 0xA1
-
-#define SPIBAR_PREOP 0xA4
-#define SPIBAR_OPTYPE 0xA6
-#define SPIBAR_OPMENU_LOWER 0xA8
-#define SPIBAR_OPMENU_UPPER 0xAc
-/* STRAP LOCK Register */
-#define SPIBAR_RESET_LOCK 0xF0
-#define SPIBAR_RESET_LOCK_DISABLE 0
-#define SPIBAR_RESET_LOCK_ENABLE 1
-/* STRAP MSG Control Register*/
-#define SPIBAR_RESET_CTRL 0xF4
-#define SPIBAR_RESET_CTRL_SSMC 1
-/* STRAP Data Register*/
-#define SPIBAR_RESET_DATA 0xF8
-
-#define SPI_FPR_MAX 5
-
-#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
-#define SPI_OPTYPE_0 0x01 /* Write, no address */
-
-#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
-#define SPI_OPTYPE_1 0x03 /* Write, address required */
-
-#define SPI_OPMENU_2 0x03 /* READ: Read Data */
-#define SPI_OPTYPE_2 0x02 /* Read, address required */
-
-#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
-#define SPI_OPTYPE_3 0x00 /* Read, no address */
-
-#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
-#define SPI_OPTYPE_4 0x03 /* Write, address required */
-
-#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
-#define SPI_OPTYPE_5 0x00 /* Read, no address */
-
-#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
-#define SPI_OPTYPE_6 0x03 /* Write, address required */
-
-#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
-#define SPI_OPTYPE_7 0x02 /* Read, address required */
-
-#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
- (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
-#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
- (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
-
-#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
- (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
- (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
- (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
-
-#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
-
-#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
-#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
-#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
-#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
-#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
-#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
-#define SPIBAR_HSFS_BERASE_MASK 3 /* Block/Sector Erase MASK */
-#define SPIBAR_HSFS_BERASE_OFFSET 3 /* Block/Sector Erase OFFSET */
-#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
-#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
-#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
-#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
-#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
-#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
-#define SPIBAR_FADDR 0x08 /* SPI flash address */
-#define SPIBAR_FADDR_MASK 0x7FFFFFF
-
-#define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */
-#define SPIBAR_FPR(n) (0x84 + (4 * n)) /* SPI flash protected range */
-#define SPIBAR_FPR_WPE (1 << 31) /* Flash Write protected */
-#define SPIBAR_SSFS 0xA0
-#define SPIBAR_SSFS_ERROR (1 << 3)
-#define SPIBAR_SSFS_DONE (1 << 2)
-#define SPIBAR_SSFC 0xA1
-#define SPIBAR_SSFC_DATA (1 << 14)
-#define SPIBAR_SSFC_GO (1 << 1)
-
-#define SPIBAR_FDOC 0xB4
-#define SPIBAR_FDOC_COMPONENT (1 << 12)
-#define SPIBAR_FDOC_FDSI_1 (1 << 2)
-
-#define SPIBAR_FDOD 0xB8
-#define FLCOMP_C0DEN_MASK 0xF
-#define FLCOMP_C0DEN_8MB 4
-#define FLCOMP_C0DEN_16MB 5
-#define FLCOMP_C0DEN_32MB 6
-
-#define SPIBAR_BIOS_CNTL 0xDC
-#define SPIBAR_BC_BILD (1 << 7)
-#define SPIBAR_BC_EISS (1 << 5)
-#define SPIBAR_BC_LE (1 << 2)
-#define SPIBAR_BC_WPD (1 << 0)
-
-void *get_spi_bar(void);
-
-#endif