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authorAaron Durbin <adurbin@chromium.org>2017-04-16 21:49:29 -0500
committerAaron Durbin <adurbin@chromium.org>2017-04-25 18:16:18 +0200
commit79f0741f815faef3bc326e97a93fd13a7652e628 (patch)
tree38803f36e7d97de9fdbd2835396d7e230c9c1372 /src/soc/intel/skylake/include
parent5e88c3b18ac7eef053d5285d6ad00c1bde4f1235 (diff)
downloadcoreboot-79f0741f815faef3bc326e97a93fd13a7652e628.tar.xz
soc/intel/skylake: use postcar stage for fsp 2.0
Utilize the postcar stage for tearing down CAR and initializing the MTRRs once ram is up. This flow is consistent with apollolake and allows CAR_GLOBAL variables to be directly accessed and no need for migrating CAR_GLOBAL variables as romstage doesn't run with and without CAR being available. Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19335 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/fsp20/soc/romstage.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
index 37e1e06fc9..6bdc3b5858 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
@@ -20,7 +20,6 @@
#include <arch/cpu.h>
#include <fsp/api.h>
-asmlinkage void *car_stage_c_entry(void);
void mainboard_memory_init_params(FSPM_UPD *mupd);
void systemagent_early_init(void);
int smbus_read_byte(unsigned int device, unsigned int address);