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authorSubrata Banik <subrata.banik@intel.com>2016-02-08 17:15:29 +0530
committerMartin Roth <martinroth@google.com>2016-03-01 20:57:45 +0100
commitb7e69a2e561d557a7d243a15d91a5cede56e5eb8 (patch)
treeba1b11d955e902083f29cee10bb04b72af419567 /src/soc/intel/skylake/include
parent2a696c07b9cdcd484800596fb850f95260419d11 (diff)
downloadcoreboot-b7e69a2e561d557a7d243a15d91a5cede56e5eb8.tar.xz
Skylake: Support Intel Speed Shift Technology based on config
Intel Speed Shift Technology is a new mechanism that replaces Legacy P-state. ISST allows OS hints about energy/performance preference. H/W performs the actual P-state control (autonomous) 1. Optimization frequency seclection for low residency workloads, no longer a static knee point. 2. Optimized frequency selection for best energy to performance trade offs. 3. Kick down frequency (from idle) fpr best responsiveness while taking energy consumption init account. Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes and enable HWP accordingly. BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu and verify HWP getting enabled/disabled using Intel P-state driver. Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313107 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: https://review.coreboot.org/13835 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/soc/msr.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h
index db154b788f..4d295e186f 100644
--- a/src/soc/intel/skylake/include/soc/msr.h
+++ b/src/soc/intel/skylake/include/soc/msr.h
@@ -36,6 +36,9 @@
#define IA32_MISC_ENABLE 0x1a0
#define MSR_MISC_PWR_MGMT 0x1aa
#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
+#define MISC_PWR_MGMT_ISST_EN (1 << 6)
+#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7)
+#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12)
#define MSR_TURBO_RATIO_LIMIT 0x1ad
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_PERF_CTL 0x199