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authorPratik Prajapati <pratikkumar.v.prajapati@intel.com>2016-11-18 14:36:34 -0800
committerMartin Roth <martinroth@google.com>2016-12-13 18:00:43 +0100
commitffc934d9440b5a8dabcedb4da0fa88d9a1e65e18 (patch)
tree2fd448d09b9a9c87ffbc6700f8ea25112f024e73 /src/soc/intel/skylake/include
parentfa97cefbb3fad90573459e57845b658c9d3351a2 (diff)
downloadcoreboot-ffc934d9440b5a8dabcedb4da0fa88d9a1e65e18.tar.xz
intel MMA: Enable MMA with FSP2.0
- Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/17496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/fsp20/soc/romstage.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
index 08753f1ee9..41658e1dbd 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
@@ -25,7 +25,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd);
void systemagent_early_init(void);
int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read_wpsr(u8 *sr);
-
/* Board type */
enum board_type {
BOARD_TYPE_MOBILE = 0,