diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-08-27 15:49:12 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-08 11:16:27 +0000 |
| commit | 08112303065bf4d8ebd009c2b5bd1364d4d872ac (patch) | |
| tree | 34958b432386205355ac19b6abf3fc774706c9f8 /src/soc/intel/skylake/include | |
| parent | 1bfbe7e72a3bb0562e190136a77f889d2cdb81f4 (diff) | |
| download | coreboot-08112303065bf4d8ebd009c2b5bd1364d4d872ac.tar.xz | |
skylake: ACPI: Fix and clean up PCIE _PRT entries
Fix the code for PCIE _PRT entries to use an actual root
port number from the device instead of NVS that was never
initialized from zero.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build and boot on glados with pci=nomsi to ensure interrupts work
Change-Id: I76ff07d2bf7001aed504558d55cca9e19c692d7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d43392199ec5f37150f2b13732924c47b8dc830c
Original-Change-Id: I1132f1dc47122db08d1b798a259ee9b52a488f5e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295902
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11529
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/nvs.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 7fef1901e2..2d8129b187 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -55,10 +55,9 @@ typedef struct { u32 cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ - u32 rpa[12]; /* 0x30 - 0x5f - Root Port Address */ - u8 dpte; /* 0x60 - Enable DPTF */ + u8 dpte; /* 0x30 - Enable DPTF */ - u8 unused[159]; + u8 unused[207]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; |