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authorSubrata Banik <subrata.banik@intel.com>2017-03-14 18:24:47 +0530
committerMartin Roth <martinroth@google.com>2017-03-28 16:40:13 +0200
commit93ebe499d45679a250de780d8a8b73d32d7ea00e (patch)
treec40c6bd71a771df26f94d028718f15ec89444afd /src/soc/intel/skylake/include
parent01ae11b057e4b15e1fde48c7845f7fbf66a4e948 (diff)
downloadcoreboot-93ebe499d45679a250de780d8a8b73d32d7ea00e.tar.xz
soc/intel/skylake: Clean up code by using common System Agent module
This patch currently contains the SA initialization required for bootblock phase - 1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code. 2. Perform PCIEXBAR programming based on soc configurable PCIEX_LENGTH_xxxMB 3. Use common systemagent header file. Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18566 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/soc/bootblock.h3
-rw-r--r--src/soc/intel/skylake/include/soc/iomap.h3
-rw-r--r--src/soc/intel/skylake/include/soc/systemagent.h14
3 files changed, 8 insertions, 12 deletions
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h
index df81d3f3fc..f290d0f668 100644
--- a/src/soc/intel/skylake/include/soc/bootblock.h
+++ b/src/soc/intel/skylake/include/soc/bootblock.h
@@ -16,6 +16,8 @@
#ifndef _SOC_SKYLAKE_BOOTBLOCK_H_
#define _SOC_SKYLAKE_BOOTBLOCK_H_
+#include <intelblocks/systemagent.h>
+
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
#include <fsp/bootblock.h>
#else
@@ -25,7 +27,6 @@ static inline void bootblock_fsp_temp_ram_init(void) {}
/* Bootblock pre console init programing */
void bootblock_cpu_init(void);
void bootblock_pch_early_init(void);
-void bootblock_systemagent_early_init(void);
void pch_uart_init(void);
/* Bootblock post console init programing */
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index e736d3b514..a6f7287f3a 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -58,6 +58,9 @@
#define HECI1_BASE_ADDRESS 0xfed1a000
+/* CPU Trace reserved memory size */
+#define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */
+
/*
* I/O port address space
*/
diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h
index c82f6913b2..c9b0bac5c7 100644
--- a/src/soc/intel/skylake/include/soc/systemagent.h
+++ b/src/soc/intel/skylake/include/soc/systemagent.h
@@ -15,9 +15,10 @@
* GNU General Public License for more details.
*/
-#ifndef _SOC_SYSTEMAGENT_H_
-#define _SOC_SYSTEMAGENT_H_
+#ifndef SOC_SKYLAKE_SYSTEMAGENT_H
+#define SOC_SKYLAKE_SYSTEMAGENT_H
+#include <intelblocks/systemagent.h>
#include <soc/iomap.h>
#define SA_IGD_OPROM_VENDEV 0x80860406
@@ -44,7 +45,6 @@
/* Device 0:0.0 PCI configuration space */
#define EPBAR 0x40
-#define MCHBAR 0x48
#define PCIEXBAR 0x60
#define DMIBAR 0x68
#define GGC 0x50 /* GMCH Graphics Control */
@@ -82,11 +82,6 @@
#define REMAPBASE 0x90 /* Remap base. */
#define REMAPLIMIT 0x98 /* Remap limit. */
#define TOM 0xa0 /* Top of DRAM in memory controller space. */
-#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
-#define BDSM 0xb0 /* Base Data Stolen Memory */
-#define BGSM 0xb4 /* Base GTT Stolen Memory */
-#define TSEG 0xb8 /* TSEG base */
-#define TOLUD 0xbc /* Top of Low Used Memory */
#define SKPAD 0xdc /* Scratchpad Data */
/* MCHBAR */
@@ -121,9 +116,6 @@
/* Data is passed through bits 31:0 of the data register. */
#define BIOS_MAILBOX_DATA 0x5da0
-/* CPU Trace reserved memory size */
-#define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */
-
/* System Agent identification */
u8 systemagent_revision(void);