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authorDuncan Laurie <dlaurie@chromium.org>2017-03-07 19:12:02 -0800
committerDuncan Laurie <dlaurie@chromium.org>2017-03-08 19:07:37 +0100
commitb2aac8503019aad122983c0b60635357e9087b9c (patch)
tree574eb4cab039609b3bd2a01ea26ab1087d8eb16f /src/soc/intel/skylake/include
parent03df460af5f73bb2fbbe23caff5f0bb646e8f756 (diff)
downloadcoreboot-b2aac8503019aad122983c0b60635357e9087b9c.tar.xz
intel/skylake: Add devicetree settings for acoustic noise mitigation
Add options to the skylake chip config that will allow tuning the various settings that can affect acoustics with the CPU and its VRs. These settings are applied inside FSP, and they can adjust the slew slew rate when changing voltages or disable fast C-state ramping on the various CPU VR rails. BUG=b:35581264 BRANCH=none TEST=these are currently unused, but I verified that enabling the options can affect the acoustics of a system at runtime. Change-Id: I6a8ec0b8d3bd38b330cb4836bfa5bbbfc87dc3fb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18662 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/skylake/include')
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