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authorSubrata Banik <subrata.banik@intel.com>2016-07-24 00:36:12 +0530
committerAndrey Petrov <andrey.petrov@intel.com>2016-07-28 05:15:58 +0200
commite4a8537ce20d801a5985ba6268ae83593063a4bf (patch)
treeefdc7dcf51a9b91f8d4f6f8db9c8a0ef951ca62d /src/soc/intel/skylake/include
parent68d5d8b28ab399b8dfb8ef6477d25311a319f2d5 (diff)
downloadcoreboot-e4a8537ce20d801a5985ba6268ae83593063a4bf.tar.xz
soc/intel/skylake: Add C entry bootblock support
List of activity performing in this patch - early PCH programming - early SA programming - early CPU programming - mainborad early gpio programming for UART and SPI - car setup - move chipset programming from verstage to post console BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and booted kunimitsu till POST code 0x34 Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15785 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r--src/soc/intel/skylake/include/soc/bootblock.h28
-rw-r--r--src/soc/intel/skylake/include/soc/romstage.h1
2 files changed, 28 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h
new file mode 100644
index 0000000000..10e1e03e22
--- /dev/null
+++ b/src/soc/intel/skylake/include/soc/bootblock.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_SKYLAKE_BOOTBLOCK_H_
+#define _SOC_SKYLAKE_BOOTBLOCK_H_
+
+/* Bootblock pre console init programing */
+void bootblock_cpu_init(void);
+void bootblock_pch_early_init(void);
+void bootblock_systemagent_early_init(void);
+
+void pch_uart_init(void);
+/* Bootblock post console init programing */
+void pch_enable_lpc(void);
+
+#endif
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index 56bace15a7..71887aa165 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -22,7 +22,6 @@
void i2c_early_init(void);
void systemagent_early_init(void);
void pch_early_init(void);
-void pch_uart_init(void);
void intel_early_me_status(void);
void report_platform_info(void);
void set_max_freq(void);