diff options
author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2017-09-28 17:06:01 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-03 20:23:21 +0000 |
commit | 1483d1fcda092283c303fd1d4f4aeca75dcd0bf1 (patch) | |
tree | 8d7fd3948634e5a8b46aaa2655a759c00843ff9c /src/soc/intel/skylake/include | |
parent | a9b5a393955d2731eb20e3312b95859a55d6230d (diff) | |
download | coreboot-1483d1fcda092283c303fd1d4f4aeca75dcd0bf1.tar.xz |
soc/intel/skylake: Enable common LPC IP
Enable Skylake to use the new common LPC code. This
will help to reduce code duplication and streamline code bring up.
Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
-rw-r--r-- | src/soc/intel/skylake/include/soc/acpi.h | 4 | ||||
-rw-r--r-- | src/soc/intel/skylake/include/soc/iomap.h | 3 | ||||
-rw-r--r-- | src/soc/intel/skylake/include/soc/lpc.h | 58 |
3 files changed, 5 insertions, 60 deletions
diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index 94c7c2ff94..b0d2194612 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -29,8 +29,8 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_mainboard_gnvs(global_nvs_t *gnvs); -void southcluster_inject_dsdt(device_t device); -unsigned long southcluster_write_acpi_tables(device_t device, +void southbridge_inject_dsdt(device_t device); +unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp); #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index de9ef97744..7e99d9984c 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -25,6 +25,9 @@ #define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define MCFG_BASE_SIZE 0x4000000 +#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 +#define PCH_PRESERVED_BASE_SIZE 0x02000000 + #define UART_DEBUG_BASE_0_SIZE 0x1000 #define UART_BASE_0_ADDRESS 0xfe030000 /* Both UART BAR 0 and 1 are 4KB in size */ diff --git a/src/soc/intel/skylake/include/soc/lpc.h b/src/soc/intel/skylake/include/soc/lpc.h deleted file mode 100644 index f3541a07c6..0000000000 --- a/src/soc/intel/skylake/include/soc/lpc.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_LPC_H_ -#define _SOC_LPC_H_ - -/* PCI Configuration Space (D31:F0): LPC */ -#define ABASE 0x40 -#define ACNTL 0x44 -#define ACPI_EN (1 << 7) -#define SCI_IRQ_SEL (7 << 0) -#define SCIS_IRQ9 0 -#define SCIS_IRQ10 1 -#define SCIS_IRQ11 2 -#define SCIS_IRQ20 4 -#define SCIS_IRQ21 5 -#define SCIS_IRQ22 6 -#define SCIS_IRQ23 7 -#define SERIRQ_CNTL 0x64 -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ -#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ -#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ -#define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ -#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ -#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ -#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ -#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ -#define LGMR 0x98 /* LPC Generic Memory Range */ -#define BIOS_CNTL 0xdc -#define LPC_BC_BILD (1 << 7) /* BILD */ -#define LPC_BC_LE (1 << 1) /* LE */ -#define LPC_BC_EISS (1 << 5) /* EISS */ -#define PCCTL 0xE0 /* PCI Clock Control */ -#define CLKRUN_EN (1 << 0) -#endif |