diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2015-07-23 17:40:32 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-19 14:04:31 +0000 |
| commit | 188e37072fbd79a7a947a903f9918a49f32a08d6 (patch) | |
| tree | b45ef3ce6c30b573be37e297f5bca7d66bfc8548 /src/soc/intel/skylake/include | |
| parent | 5c1c3d69dd47e11bea2e3f61eeb17ed13e5a8e0d (diff) | |
| download | coreboot-188e37072fbd79a7a947a903f9918a49f32a08d6.tar.xz | |
Skylake: update cbmem_top
cbmem_top was using CHIPSET_RESERVED_MEM_BYTES to w/a unknown memory
regions reserved by fsp for chipset use. With that being removed, the
function needs to properly walk though the memory map resulted from fsp
memory init to find out the usable address for cbmem root.
Refer the FSP 1.3.0 Integartion guide for more details on the Memory
Map.
systemagent should also use the same mechanism to create the reserved
RAM resource.
BRANCH=None
BUG=None
TEST=Build and Boot kunimitsu (FAB3)
CQ-DEPEND=CL:*226035,CL:*226045,CL:291573
Original-Change-Id: Id0954cf8e6388e549c7d4df67b468572b5bea539
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291611
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com>
Change-Id: I4e716170f40936081ce9d4878bf74c75f469f78d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: http://review.coreboot.org/11239
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/msr.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/systemagent.h | 6 |
2 files changed, 8 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 390375703e..4239b36996 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -54,8 +54,8 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_POWER_CTL 0x1fc #define MSR_LT_LOCK_MEMORY 0x2e7 -#define UNCORE_EMRR_PHYS_BASE_MSR 0x2f4 -#define UNCORE_EMRR_PHYS_MASK_MSR 0x2f5 +#define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 +#define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 #define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 6bb5c66d2a..59221c7754 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -120,7 +120,13 @@ /* Data is passed through bits 31:0 of the data register. */ #define BIOS_MAILBOX_DATA 0x5da0 +/* CPU Trace reserved memory size */ +#define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */ + /* System Agent identification */ u8 systemagent_revision(void); +/* Top of 32bit usable memory */ +u32 top_of_32bit_ram(void); + #endif |