diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2016-10-18 14:25:25 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-10-26 08:33:37 +0200 |
| commit | 3bfe3404df32ca226c624be0435c640bf1ebeae7 (patch) | |
| tree | 0eef45f9ad972dec851f902d84470cb0b54c3cbf /src/soc/intel/skylake/include | |
| parent | ffb3a2d22506a86e205a757029f60abccfef0486 (diff) | |
| download | coreboot-3bfe3404df32ca226c624be0435c640bf1ebeae7.tar.xz | |
intel/skylake: Add support to enable wake-on-usb attach/detach
Three things are required to enable wake-on-usb:
1. 5V to USB ports should be enabled in S3.
2. ASL file needs to have appropriate wake bit set.
3. XHCI controller should have the wake on attach/detach bit set for the
corresponding port in PORTSCN register.
Only part missing was #3.
This CL adds support to allow mainboard to define a bitmap in
devicetree corresponding to the ports that it wants to enable
wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in
PORTSCN would be set by xhci.asl for the appropriate ports.
BUG=chrome-os-partner:58734
BRANCH=None
TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb
attach/detach.
Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17056
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/nvs.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/usb.h | 7 |
2 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index f9d5b71880..cb3b2c6ee5 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -54,7 +54,9 @@ typedef struct { u64 nhla; /* 0x31 - NHLT Address */ u32 nhll; /* 0x39 - NHLT Length */ u16 cid1; /* 0x3d - Wifi Country Identifier */ - u8 unused[193]; + u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */ + u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */ + u8 unused[190]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index e5b0495f05..a18e79ce66 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -169,4 +169,11 @@ struct usb3_port_config { .tx_downscale_amp = 0x00, \ } +/* + * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds + * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to + * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. + */ +#define USB_PORT_WAKE_ENABLE(x) (1 << (x - 1)) + #endif |