diff options
| author | david <david_wu@quantatw.com> | 2015-12-29 15:02:04 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-09 19:44:57 +0100 |
| commit | 4852dec1ab21e6c6e32eb85354ce4f4182537442 (patch) | |
| tree | 42ae4e8c398d9f2ec7cdc9f3018c319e36acf655 /src/soc/intel/skylake/include | |
| parent | 1c85fea945307404546ac953a65329b2b37aec36 (diff) | |
| download | coreboot-4852dec1ab21e6c6e32eb85354ce4f4182537442.tar.xz | |
intel/skylake: Add gpio macro for unused GPIO pins
Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
GPIO TX/RX will be disabled.
BUG=none
BRANCH=none
TEST=Build and boot lars
Change-Id: I3a6fcd2f3462e8e0d1273aa80b1599b76b160825
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 889bfd66dbc918e9fb0ba1b95b63fd7a3bf180d9
Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319964
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/13628
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/gpio.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 7dec874048..f2246e9116 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -108,6 +108,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); _PAD_CFG(pad_, term_, \ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO)) +/* Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and + GPIO TX/RX will be disabled. */ +#define PAD_CFG_NC(pad_) \ + _PAD_CFG(pad_, NONE, \ + _DW0_VALS(DEEP, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, YES)) + /* General purpose output with termination. */ #define PAD_CFG_TERM_GPO(pad_, val_, term_, rst_) \ _PAD_CFG(pad_, term_, \ |