diff options
| author | Archana Patni <archana.patni@intel.com> | 2015-11-11 01:29:23 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-17 22:54:17 +0100 |
| commit | 7846e34c02473a2a000e1fda1e2051475ef3fbf1 (patch) | |
| tree | dba3417a968fa94dd241cbcd85be65eb5975b9fb /src/soc/intel/skylake/include | |
| parent | df13c31ed6fdad2cdb6e8e874f26e5cad2ce935f (diff) | |
| download | coreboot-7846e34c02473a2a000e1fda1e2051475ef3fbf1.tar.xz | |
intel/skylake: disable heci1 if psf is unlocked
This patch adds support for disabling the heci1 device
at the end of boot sequence. Prior to this, FSP would have
sent the end of post message to ME and initiated the d0i3 bit.
This uses the Psf unlock policy and the p2sb device to disable
the heci1 device, then lock the configuration and hide the device.
BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu or glados board. set the hecienabled policy
to 0 and check for heci 1 device status in kernel lspci.
CQ-DEPEND=CL:*238451
Change-Id: I26b145231f8ed0c140af42d378b222e857d9aff6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fe184b8baf1bea9bcd0af1841785a4d763af9358
Original-Change-Id: I3b435491aeea0f2ca36b7877e942dc940560e4dd
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311912
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12976
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pci_devs.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pcr.h | 6 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 5ce2136a8c..2dba3dec20 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -127,6 +127,7 @@ #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) #define PCH_DEVFN_HDA _PCH_DEVFN(LPC, 3) #define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) @@ -134,6 +135,7 @@ #define PCH_DEVFN_GBE _PCH_DEVFN(LPC, 6) #define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) +#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) #define PCH_DEV_PMC _PCH_DEV(LPC, 2) #define PCH_DEV_HDA _PCH_DEV(LPC, 3) #define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h index cb64af6578..8a46cd1e5e 100644 --- a/src/soc/intel/skylake/include/soc/pcr.h +++ b/src/soc/intel/skylake/include/soc/pcr.h @@ -83,6 +83,7 @@ #define PID_GPIOCOM2 0xAD #define PID_GPIOCOM1 0xAE #define PID_GPIOCOM0 0xAF +#define PID_PSF1 0xBA #define PID_SCS 0xC0 #define PID_RTC 0xC3 #define PID_ITSS 0xC4 @@ -90,6 +91,11 @@ #define PID_SERIALIO 0xCB #define PID_DMI 0xEF +#define PCH_PCR_PSFX_T0_SHDW_PCIEN 0x1C + +#define PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) +#define PSF_BASE_ADDRESS 0xA00 + #if !defined(__ASSEMBLER__) && !defined(__ACPI__) #include <stdint.h> |