diff options
| author | Robbie Zhang <robbie.zhang@intel.com> | 2017-02-21 14:00:31 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-23 19:57:17 +0100 |
| commit | 7de031759b916bbb91e74e6eea371b5ca87e6bd5 (patch) | |
| tree | 3a21679ac510c4fb68f88ea8dae4cd1537231ff6 /src/soc/intel/skylake/include | |
| parent | 08d808ff3d2f4ed373fd7390cbf16a63bbe6a7d5 (diff) | |
| download | coreboot-7de031759b916bbb91e74e6eea371b5ca87e6bd5.tar.xz | |
soc/intel/skylake: Add SGX initialization
This patch implements SGX initialization steps in coreboot per Intel SGX
BWG rev 2.0.8 for Kaby Lake SoC. If enabled on a Kabylake device, SoC
capability and PRM (processor reserved memory) of desired size (needs to
be configured through PrmrrSize) are provisioned for later software
stack to use SGX (i.e., run SGX enclaves).
One issue is still puzzling and needs to be addressed: by calling
configure_sgx() in cpu_core_init() which is the per-thread function, SGX
is always failing for thread 0 but is successful for other 3 threads.
I had to call configure_sgx() again from soc_init_cpus() which is the
BSP-only function to make it enable on the BSP.
Another pending work is the implementation for the Owner Epoch update
which shall be added later.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified SGX activation is successful on all threads.
Change-Id: I8b64284875eae061fa8e7a01204d48d320a285a9
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18445
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/cpu.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/msr.h | 10 |
2 files changed, 8 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 33fb2f1b3a..a259a2bafb 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -68,5 +68,6 @@ u32 cpu_family_model(void); u32 cpu_stepping(void); int cpu_is_ult(void); int is_secondary_thread(void); +void configure_sgx(const void *microcode_patch); #endif diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index a5724477cc..36eefdb7b0 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -20,6 +20,7 @@ #include <intelblocks/msr.h> #define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_BIOS_UPGD_TRIG 0x7a #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) @@ -29,13 +30,16 @@ #define ENERGY_POLICY_NORMAL 6 #define ENERGY_POLICY_POWERSAVE 15 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define EMRR_PHYS_BASE_MSR 0x1f4 -#define EMRR_PHYS_MASK_MSR 0x1f5 +#define PRMRR_PHYS_BASE_MSR 0x1f4 +#define PRMRR_PHYS_MASK_MSR 0x1f5 +#define PRMRR_PHYS_MASK_LOCK (1 << 10) +#define PRMRR_PHYS_MASK_VALID (1 << 11) #define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_LT_LOCK_MEMORY 0x2e7 #define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 #define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 - +#define MSR_SGX_OWNEREPOCH0 0x300 +#define MSR_SGX_OWNEREPOCH1 0x301 #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 #define MSR_VR_MISC_CONFIG2 0x636 |