diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-09-28 19:54:30 +0530 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-10-09 20:10:00 +0000 |
| commit | 46caf09598575747070c599dbfd9abca9e96b831 (patch) | |
| tree | b739206d82166f6d514b70af59fd7fa953ae98ad /src/soc/intel/skylake/include | |
| parent | 1f33a0c799bac60b5bcc24481303ebbcdaf0e7d2 (diff) | |
| download | coreboot-46caf09598575747070c599dbfd9abca9e96b831.tar.xz | |
soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers
This patch save and restore ITSS IPCx register before and after
FSP-S call.
Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/itss.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/itss.h b/src/soc/intel/skylake/include/soc/itss.h index 5ff9bb1e55..e6eb8b0744 100644 --- a/src/soc/intel/skylake/include/soc/itss.h +++ b/src/soc/intel/skylake/include/soc/itss.h @@ -16,6 +16,9 @@ #ifndef SOC_INTEL_SKL_ITSS_H #define SOC_INTEL_SKL_ITSS_H +#define GPIO_IRQ_START 50 +#define GPIO_IRQ_END ITSS_MAX_IRQ + #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) |