diff options
author | Subrata Banik <subrata.banik@intel.com> | 2018-05-28 16:12:03 +0530 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-06-07 21:58:19 +0000 |
commit | 9cd99a1524cd8c7cd6100cfc9d68e85eea5ac265 (patch) | |
tree | b5eaea43ae458551051d1f42d952603e60b98d49 /src/soc/intel/skylake/lockdown.c | |
parent | 6994bfefb59304140e6b65d4d71e0719b104d257 (diff) | |
download | coreboot-9cd99a1524cd8c7cd6100cfc9d68e85eea5ac265.tar.xz |
soc/intel/common/pch: Add pch lockdown code
pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.
Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/lockdown.c')
-rw-r--r-- | src/soc/intel/skylake/lockdown.c | 70 |
1 files changed, 6 insertions, 64 deletions
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index fd1f5b2206..e4818dc212 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,24 +14,15 @@ */ #include <arch/io.h> -#include <bootstate.h> -#include <chip.h> #include <intelblocks/chip.h> -#include <intelblocks/fast_spi.h> #include <intelblocks/lpc_lib.h> -#include <intelblocks/pcr.h> -#include <soc/pci_devs.h> -#include <soc/pcr_ids.h> +#include <intelpch/lockdown.h> #include <soc/pm.h> -#include <string.h> -#define PCR_DMI_GCS 0x274C -#define PCR_DMI_GCS_BILD (1 << 0) - -static void lpc_lockdown_config(const struct soc_intel_common_config *config) +static void lpc_lockdown_config(int chipset_lockdown) { /* Set Bios Interface Lock, Bios Lock */ - if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { lpc_set_bios_interface_lock_down(); lpc_set_lock_enable(); } @@ -49,60 +40,11 @@ static void pmc_lockdown_config(void) write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); } -static void dmi_lockdown_config(void) +void soc_lockdown_config(int chipset_lockdown) { - /* - * GCS reg of DMI - * - * When set, prevents GCS.BBS from being changed - * GCS.BBS: (Boot BIOS Strap) This field determines the destination - * of accesses to the BIOS memory range. - * Bits Description - * "0b": SPI - * "1b": LPC/eSPI - */ - pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); -} - -static void fast_spi_lockdown_config(const - struct soc_intel_common_config *config) -{ - /* Set FAST_SPI opcode menu */ - fast_spi_set_opcode_menu(); - - /* Discrete Lock Flash PR registers */ - fast_spi_pr_dlock(); - - /* Lock FAST_SPIBAR */ - fast_spi_lock_bar(); - - /* Set Bios Interface Lock, Bios Lock */ - if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { - /* Bios Interface Lock */ - fast_spi_set_bios_interface_lock_down(); - - /* Bios Lock */ - fast_spi_set_lock_enable(); - } -} - -static void platform_lockdown_config(void *unused) -{ - const struct soc_intel_common_config *common_config; - common_config = chip_get_common_soc_structure(); - /* LPC lock down configuration */ - lpc_lockdown_config(common_config); - - /* SPI lock down configuration */ - fast_spi_lockdown_config(common_config); - - /* DMI lock down configuration */ - dmi_lockdown_config(); + lpc_lockdown_config(chipset_lockdown); /* PMC lock down configuration */ pmc_lockdown_config(); } - -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config, - NULL); |