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| author | V Sowmya <v.sowmya@intel.com> | 2017-11-27 11:31:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2017-11-30 06:38:44 +0000 |
| commit | c333b98fb8a29f822978dd98e458fa13c1ba3a16 (patch) | |
| tree | 683b4cf1ed1347c657cdeb0711a440879584293c /src/soc/intel/skylake/lpc.c | |
| parent | a3a84565afef26f918d4ff2d80e0201be671c0b9 (diff) | |
| download | coreboot-c333b98fb8a29f822978dd98e458fa13c1ba3a16.tar.xz | |
soc/intel/common: Add Intel SRAM common code support
Add SRAM code support in intel/common/block to read
and use fixed resources on BAR0 and BAR2 for SRAM.
Change-Id: I7870a3ca09ac7b57eb551d5eb42d8361d22f362a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/22607
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/lpc.c')
0 files changed, 0 insertions, 0 deletions