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author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-05-12 18:19:47 -0700 |
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committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-16 17:23:27 +0200 |
commit | b000513741d330947bb832a5835378e35bdfb394 (patch) | |
tree | 0e039f881e195633b53c46424394715fff35558f /src/soc/intel/skylake/memmap.c | |
parent | 741a0dd89ce67d0fed9a7907bb77ed3ea9afba81 (diff) | |
download | coreboot-b000513741d330947bb832a5835378e35bdfb394.tar.xz |
soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC
Use the Broadwell implementation as the comparison base for Skylake.
BRANCH=none
BUG=None
TEST=None
Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10340
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/memmap.c')
-rw-r--r-- | src/soc/intel/skylake/memmap.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c new file mode 100644 index 0000000000..7b8df28f71 --- /dev/null +++ b/src/soc/intel/skylake/memmap.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <soc/pci_devs.h> +#include <soc/systemagent.h> + +static uintptr_t dpr_region_start(void) +{ + /* + * Base of DPR is top of usable DRAM below 4GiB. The register has + * 1 MiB alignment and reports the TOP of the range, the base + * must be calculated from the size in MiB in bits 11:4. + */ + uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR); + uintptr_t tom = dpr & ~((1 << 20) - 1); + + /* Subtract DMA Protected Range size if enabled */ + if (dpr & DPR_EPM) + tom -= (dpr & DPR_SIZE_MASK) << 16; + + return tom; +} + +void *cbmem_top(void) +{ + return (void *) dpr_region_start(); +} |