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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-09-17 11:50:39 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@gmail.com> | 2015-10-11 23:57:53 +0000 |
| commit | f45eb062da5a78425d52732b0a0a988b30457c24 (patch) | |
| tree | bbf55e6866ac925954aee49a2d9b8b2915854de7 /src/soc/intel/skylake/pch.c | |
| parent | b593366e349673cd4ef5b933849f78e6e958d626 (diff) | |
| download | coreboot-f45eb062da5a78425d52732b0a0a988b30457c24.tar.xz | |
skylake: SPI code cleanup
Move base address into iomap.h. Use PCI symbols instead of SPI specific
symbols. Fix comments.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Change-Id: Id5d21603150b52fd1b71dd448105938bd6aff1a9
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11826
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/pch.c')
| -rw-r--r-- | src/soc/intel/skylake/pch.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/pch.c b/src/soc/intel/skylake/pch.c index 8657402ab8..beaa7bc8a7 100644 --- a/src/soc/intel/skylake/pch.c +++ b/src/soc/intel/skylake/pch.c @@ -45,11 +45,11 @@ void *get_spi_bar(void) device_t dev = PCH_DEV_SPI; uint32_t bar; - bar = pci_read_config32(dev, PCH_SPI_BASE_ADDRESS); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); /* Bits 31-12 are the base address as per EDS for SPI 1F/5, * Don't care about 0-11 bit */ - return (void *)(bar & ~(B_PCH_SPI_BAR0_MASK)); + return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); } u32 pch_read_soft_strap(int id) |