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authorSubrata Banik <subrata.banik@intel.com>2017-12-19 10:27:45 +0530
committerSubrata Banik <subrata.banik@intel.com>2017-12-21 03:48:13 +0000
commit7f4ec968695e918da49fc9b9163188188b71f05b (patch)
tree7a6ad392a585451eec8086562cea9fa44e06a5e6 /src/soc/intel/skylake/pmc.c
parent9b98febe7a9126ab4a323c8eeedb1427e959f7d9 (diff)
downloadcoreboot-7f4ec968695e918da49fc9b9163188188b71f05b.tar.xz
soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS
TEST=KBL_RVP is able to power on after reconnecting power supply. Change-Id: Ic707164a576ffb25418eb6553843cd8edc608800 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/pmc.c')
-rw-r--r--src/soc/intel/skylake/pmc.c62
1 files changed, 44 insertions, 18 deletions
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index 91b319c55b..92d0f9e358 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -73,43 +73,58 @@ static const struct reg_script pmc_write1_to_clear_script[] = {
REG_SCRIPT_END
};
+/*
+ * Set which power state system will be after reapplying
+ * the power (from G3 State)
+ */
+static void pmc_set_afterg3(struct device *dev, int s5pwr)
+{
+ uint8_t reg8;
+
+ reg8 = pci_read_config8(dev, GEN_PMCON_B);
+
+ switch (s5pwr) {
+ case MAINBOARD_POWER_STATE_OFF:
+ reg8 |= 1;
+ break;
+ case MAINBOARD_POWER_STATE_ON:
+ reg8 &= ~1;
+ break;
+ case MAINBOARD_POWER_STATE_PREVIOUS:
+ default:
+ break;
+ }
+
+ pci_write_config8(dev, GEN_PMCON_B, reg8);
+}
+
static void pch_power_options(struct device *dev)
{
- u16 reg16;
const char *state;
/* Get the chip configuration */
- int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on = pmc_get_mainboard_power_failure_state_choice();
/*
* Which state do we want to goto after g3 (power restored)?
- * 0 == S0 Full On
- * 1 == S5 Soft Off
- *
- * If the option is not existent (Laptops), use Kconfig setting.
+ * 0 == S5 Soft Off
+ * 1 == S0 Full On
+ * 2 == Keep Previous State
*/
- /*TODO: cmos_layout.bin need to verify; cause wrong CMOS setup*/
- //get_option(&pwr_on, "power_on_after_fail");
- pwr_on = MAINBOARD_POWER_ON;
- reg16 = pci_read_config16(dev, GEN_PMCON_B);
- reg16 &= 0xfffe;
switch (pwr_on) {
- case MAINBOARD_POWER_OFF:
- reg16 |= 1;
+ case MAINBOARD_POWER_STATE_OFF:
state = "off";
break;
- case MAINBOARD_POWER_ON:
- reg16 &= ~1;
+ case MAINBOARD_POWER_STATE_ON:
state = "on";
break;
- case MAINBOARD_POWER_KEEP:
- reg16 &= ~1;
+ case MAINBOARD_POWER_STATE_PREVIOUS:
state = "state keep";
break;
default:
state = "undefined";
}
- pci_write_config16(dev, GEN_PMCON_B, reg16);
+ pmc_set_afterg3(dev, pwr_on);
printk(BIOS_INFO, "Set power %s after power failure.\n", state);
/* Set up GPE configuration. */
@@ -178,4 +193,15 @@ void pmc_soc_init(struct device *dev)
/* Clear registers that contain write-1-to-clear bits. */
reg_script_run_on_dev(dev, pmc_write1_to_clear_script);
}
+
+/*
+ * Set PMC register to know which state system should be after
+ * power reapplied
+ */
+void pmc_soc_restore_power_failure(void)
+{
+ pmc_set_afterg3(PCH_DEV_PMC,
+ pmc_get_mainboard_power_failure_state_choice());
+}
+
#endif