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authorHannah Williams <hannah.williams@intel.com>2017-04-06 20:54:11 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-02 22:32:33 +0000
commit1760cd3eb44ad123b6d3e3e295cdbf43f9465db1 (patch)
tree25d37433765d4824d41075b39bb7396e9f0a504b /src/soc/intel/skylake/pmutil.c
parenta05fdcb2695a9d7c553c23ef6c35c37d7cd7b795 (diff)
downloadcoreboot-1760cd3eb44ad123b6d3e3e295cdbf43f9465db1.tar.xz
soc/intel/skylake: Use common/block/gpio
Other than switch to use common gpio implementation for skylake based platform, also apply the needed changes for purism board. Change-Id: I06e06dbcb6d0d6fe277dfad57b82aca51f94b099 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/pmutil.c')
-rw-r--r--src/soc/intel/skylake/pmutil.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 2a677fda74..36e4784a10 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -536,7 +536,9 @@ void pmc_gpe_init(void)
write32(pmc_regs + GPIO_CFG, gpio_cfg_reg);
/* Set the routes in the GPIO communities as well. */
- gpio_route_gpe(gpio_cfg_reg >> GPE0_DW0_SHIFT);
+ gpio_route_gpe((gpio_cfg_reg >> GPE0_DW0_SHIFT) & GPE0_DWX_MASK,
+ (gpio_cfg_reg >> GPE0_DW1_SHIFT) & GPE0_DWX_MASK,
+ (gpio_cfg_reg >> GPE0_DW2_SHIFT) & GPE0_DWX_MASK);
/* Set GPE enables based on devictree. */
enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,