diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2015-10-05 19:11:39 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-27 15:15:39 +0100 |
| commit | 952cb03b9e08883da46fb57f99aec919f5a9b60a (patch) | |
| tree | da6bb212c26c33607b8d18a318b6f3296ae9dac0 /src/soc/intel/skylake/romstage/romstage.c | |
| parent | e57e72681fa218bb747f658576c64111c20363e3 (diff) | |
| download | coreboot-952cb03b9e08883da46fb57f99aec919f5a9b60a.tar.xz | |
intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params update
In FSP 1.7.0 SataMode and SataEnable have been moved from
MemoryInit to SiliconInit. Also, GpioTablePtr has been removed.
USB phy settings added to SiliconInit, Enable the configs for USB
equalization settings in coreboot.
Addition of serialIO UPD to indicate FSP not to reinitialise
UART2 controller during MemoryInit.
BRANCH=none BUG=chrome-os-partner:45684, chrome-os-partner:42284, chrome-os-partner:41374
TEST=build for Kunimitsu, boot on FAB3, Also checked for Boot from USB, Boot from eMMC,
USB Audio, Onboard Audio, Touch, Wifi, S3 entry/resume
CQ-DEPEND=CL:*232947, CL:*232946, CL:*232948, CL:*232949
Change-Id: I2e8e6e32fc7074774ddcf1fb4c270bb56372b7df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 623c5a52f3afedaf2c0bfe7361cfd627d093cb73
Original-Change-Id: I8b3be2c49893c564fe2197aa32bde6323bf425e9
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303661
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12144
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/skylake/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index b21eb8a304..3c60b163fa 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -101,11 +101,10 @@ void soc_memory_init_params(struct romstage_params *params, upd->IedSize = CONFIG_IED_REGION_SIZE; upd->ProbelessTrace = config->ProbelessTrace; upd->EnableLan = config->EnableLan; - upd->EnableSata = config->EnableSata; - upd->SataMode = config->SataMode; upd->EnableTraceHub = config->EnableTraceHub; upd->SaGv = config->SaGv; upd->RMT = config->Rmt; + upd->Cio2Enable = config->Cio2Enable; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, @@ -233,9 +232,6 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, soc_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize); soc_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize); soc_display_upd_value("EnableLan", 1, old->EnableLan, new->EnableLan); - soc_display_upd_value("EnableSata", 1, old->EnableSata, - new->EnableSata); - soc_display_upd_value("SataMode", 1, old->SataMode, new->SataMode); soc_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub, new->EnableTraceHub); soc_display_upd_value("PcieRpEnable[0]", 1, old->PcieRpEnable[0], @@ -406,6 +402,7 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, new->ApertureSize); soc_display_upd_value("SaGv", 1, old->SaGv, new->SaGv); soc_display_upd_value("RMT", 1, old->RMT, new->RMT); + soc_display_upd_value("Cio2Enable", 1, old->Cio2Enable, new->Cio2Enable); } /* SOC initialization after RAM is enabled. */ |