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| author | Angel Pons <th3fanbus@gmail.com> | 2019-08-30 20:05:33 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-27 13:45:49 +0000 |
| commit | 4ff63d3a11014fa1a54c82a3023182059c5812f1 (patch) | |
| tree | ce2075a44885403f46266950a6e8998db7db6bd0 /src/soc/intel/skylake/romstage/romstage.c | |
| parent | 941796a50d1ed3cefd503aa28b97be14e22273bb (diff) | |
| download | coreboot-4ff63d3a11014fa1a54c82a3023182059c5812f1.tar.xz | |
soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot
Do it in coreboot code instead of letting FSP do it.
Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/skylake/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2904f05f01..d381caa104 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -248,12 +248,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, cpu_flex_override(m_cfg); - if (!config->ignore_vtd) { - m_cfg->PchHpetBdfValid = 1; - m_cfg->PchHpetBusNumber = V_P2SB_HBDF_BUS; - m_cfg->PchHpetDeviceNumber = V_P2SB_HBDF_DEV; - m_cfg->PchHpetFunctionNumber = V_P2SB_HBDF_FUN; - } + /* HPET BDF already handled in coreboot code, so tell FSP to ignore UPDs */ + m_cfg->PchHpetBdfValid = 0; + m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING); } |