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author | Meera Ravindranath <meera.ravindranath@intel.com> | 2020-07-21 19:12:53 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2020-08-18 13:56:27 +0000 |
commit | d980339aca2aa63a946696211645cdd4968f4bbe (patch) | |
tree | 2b936a253fdb4ea333cf65ea5869416a5ed718b4 /src/soc/intel/skylake/romstage/romstage.c | |
parent | 6aa6f1f874c26c7d47c579d5adca0d866b8b0ee4 (diff) | |
download | coreboot-d980339aca2aa63a946696211645cdd4968f4bbe.tar.xz |
soc/intel/jasperlake: Fix PMC_GPE_DW mapping
PMC_GPE_DW mapping was not configured correctly and hence
coreboot skipped programming Tier 1 GPIOs resulting in failure of
S3 wake from Trackpad.
TEST=System should wake from S3 via trackpad
Change-Id: I59ce3720e0ffeefb2c9440bb300689def80211ea
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/soc/intel/skylake/romstage/romstage.c')
0 files changed, 0 insertions, 0 deletions