diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-04-02 08:49:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-08 14:11:21 +0000 |
| commit | 7935b4a89b5bf9118b2d3a3fc7a1dbde6dc7af23 (patch) | |
| tree | 35c2b34e3dd54064017c7bd784c2878c3f26a24d /src/soc/intel/skylake/romstage/romstage_fsp20.c | |
| parent | 83bb2d44b59a77c174bc8d57822e2885bbfcae83 (diff) | |
| download | coreboot-7935b4a89b5bf9118b2d3a3fc7a1dbde6dc7af23.tar.xz | |
siemens/mc_apl5: Remove reduced clock rate for I2C0
There is no device on I2C0 which requires a lower clock rate.
Change-Id: Iaf01be5ea4839c54eb2f0ba95bca272970c24bdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/skylake/romstage/romstage_fsp20.c')
0 files changed, 0 insertions, 0 deletions