diff options
| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2019-04-03 11:21:17 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-08 14:12:15 +0000 |
| commit | a12e9b0666e1a22958ea1fae87199a8b82266ee7 (patch) | |
| tree | 740c9a55c61e3a698492689b4661ef90befc023d /src/soc/intel/skylake/romstage/romstage_fsp20.c | |
| parent | 7935b4a89b5bf9118b2d3a3fc7a1dbde6dc7af23 (diff) | |
| download | coreboot-a12e9b0666e1a22958ea1fae87199a8b82266ee7.tar.xz | |
soc/skl: Update SkipExtGfxScan in UPD from devtree
The SkipExtGfxScan option is defined in the device tree, but doesn`t
update the value in the UPD. It uses the default value - 0. This
means that the FSP will scan all external graphics devices, in spite
of the configuration in devicetree.cb for a specific board.
Patch updates SkipExtGfxScan options in UPD from devicetree.cb.
This change affects all boards with skl/kbl processor.
Change-Id: Ie88a41bdf31f7c3e88df6c70c82a1cbf866372c4
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/skylake/romstage/romstage_fsp20.c')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index d9b2706a8b..dcfc3632ca 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -354,6 +354,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) /* Set primary graphic device */ soc_primary_gfx_config_params(m_cfg, config); + m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan; mainboard_memory_init_params(mupd); } |