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author | Andrey Petrov <andrey.petrov@intel.com> | 2016-11-18 14:57:51 -0800 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2016-11-30 16:45:29 +0100 |
commit | f796c6e0ec6769873d63b6fcfc64c0ac14ba3555 (patch) | |
tree | 75ea5fdb98fd06d332549e55304295a21fee30ef /src/soc/intel/skylake/romstage | |
parent | 51c67601f16899cac0b860b80b76ee674e135faa (diff) | |
download | coreboot-f796c6e0ec6769873d63b6fcfc64c0ac14ba3555.tar.xz |
driver/intel/fsp2_0: Add version parameter to FSP platform callback
Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17497
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
-rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8e083234a0..adb84423ac 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -132,7 +132,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) m_cfg->PcieRpEnableMask = mask; } -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; |