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author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-19 11:57:05 +0200 |
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committer | Nico Huber <nico.h@gmx.de> | 2019-11-04 19:10:08 +0000 |
commit | 68da45479fd289281017768a8cfa51b2f642ac07 (patch) | |
tree | b5ca58b442f84b92b2b07803736497d29c835aea /src/soc/intel/skylake/romstage | |
parent | 1644e4898535918dcd3f0225792b63a4441bda91 (diff) | |
download | coreboot-68da45479fd289281017768a8cfa51b2f642ac07.tar.xz |
soc/intel: skl,cnl,icl: rely on TOLUM as cbmem_top returned by FSP
Instead of doing our own calculations, rely on TOLUM returned by FSP
for cbmem_top. This (hopefully) saves us from making mistakes in weird
calculations of offsets and alignments.
Further this makes it easier to implement e.g. SGX PRMRR size selection
via Kconfig as we do not have to make any assumptions about alignments
but can simply pass (valid) values to FSP.
Tested successfully on X11SSM-F
Change-Id: If66a00d1320917bc68afb32c19db0e24c6732812
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36136
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
0 files changed, 0 insertions, 0 deletions