soc/intel/skylake: Use the new SPI driver interface

1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash
controller in different files.

BUG=chrome-os-partner:59832
BRANCh=None
TEST=Compiles successfully for chell and eve.

Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17933
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 40 insertions, 0 deletions

diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c
new file mode 100644
index 0000000000..a8a83c6f31
--- /dev/null
+++ b/src/soc/intel/skylake/spi.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <spi-generic.h>
+
+/* SPI controller managing the flash-device SPI. */
+static int flash_spi_ctrlr_setup(const struct spi_slave *dev)
+{
+	if ((dev->bus != 0) || (dev->cs != 0)) {
+		printk(BIOS_ERR, "%s: Unsupported device bus=0x%x,cs=0x%x!\n",
+			__func__, dev->bus, dev->cs);
+		return -1;
+	}
+
+	return 0;
+}
+
+static const struct spi_ctrlr flash_spi_ctrlr = {
+	.setup = flash_spi_ctrlr_setup,
+};
+
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+	{ .ctrlr = &flash_spi_ctrlr, .bus_start = 0, .bus_end = 0 },
+};
+
+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);