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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-04-24 17:42:49 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2020-05-04 22:46:21 +0000 |
| commit | 65cc80f740a736d3b947268c157d3331a7cec922 (patch) | |
| tree | 5850cf33b4017dd4f354f3dd8fbf83517ad8d307 /src/soc/intel/skylake/uart.c | |
| parent | 6ad8352a3de78e2f6869cc7fbc4274057fcffd4a (diff) | |
| download | coreboot-65cc80f740a736d3b947268c157d3331a7cec922.tar.xz | |
soc/intel/tigerlake: Update interrupt setting
Update interrupt setting based on latest FSP(3163.01)
Reference:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c
BUG=b:155315876
BRANCH=none
TEST=Build with new FSP(3163.01) and boot OS and login OS console
in ripto/volteer. Without this change, we can't login due to mismatch
interrupt setting between asl and fsp setting.
Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40872
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/uart.c')
0 files changed, 0 insertions, 0 deletions