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| author | Sooi, Li Cheng <li.cheng.sooi@intel.com> | 2017-01-04 13:36:06 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-02-16 05:09:13 +0100 |
| commit | c76e9982b231023ccf91b79ec7526e50f595ffc1 (patch) | |
| tree | 31ec30fe5f48efbc92a5e17385687892a0e20e9f /src/soc/intel/skylake/xhci.c | |
| parent | 901efea8abbb3131685fd69fd4ad7c5093c8cb3c (diff) | |
| download | coreboot-c76e9982b231023ccf91b79ec7526e50f595ffc1.tar.xz | |
soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC
Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC
Change-Id: I6a44d55d1588d2620bd1179ea7dc327922f49fd7
Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com>
Reviewed-on: https://review.coreboot.org/18028
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/skylake/xhci.c')
| -rw-r--r-- | src/soc/intel/skylake/xhci.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c index 6b4a19a3dd..5ee34dfc68 100644 --- a/src/soc/intel/skylake/xhci.c +++ b/src/soc/intel/skylake/xhci.c @@ -33,6 +33,7 @@ static struct device_operations usb_xhci_ops = { static const unsigned short pci_device_ids[] = { 0x9d2f, /* SunRisePoint LP */ + 0xa12f, /* KBL-H*/ 0 }; |