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| author | Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> | 2018-10-04 16:17:22 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-10-05 16:36:35 +0000 |
| commit | 4f6eccdcac841f48a6a4bac846840e2cb79a4ff3 (patch) | |
| tree | 7cd066c061d733aaee85231760c8fbd8543301d4 /src/soc/intel/skylake | |
| parent | f97ff0cd503eb254432848e0f6ec6b6c2a15ce47 (diff) | |
| download | coreboot-4f6eccdcac841f48a6a4bac846840e2cb79a4ff3.tar.xz | |
mb/google/octopus: adjust Bobba I2C CLK under 400KHz
Need to tune I2C bus 0/6/7 clock frequency under the 400KHz for
digitizer, touchpad, and touchscreen.
Bug=b:117126484
TEST=flash coreboot to the DUT and measure I2C bus 0/6/7 clock
frequency whether can <400KHz
Change-Id: Icb9592c688b864a21efd4963a4463845dfaa06fb
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28907
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
0 files changed, 0 insertions, 0 deletions