summaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake
diff options
context:
space:
mode:
authorMaxim Polyakov <max.senia.poliak@gmail.com>2019-10-03 16:50:04 +0300
committerPatrick Georgi <pgeorgi@google.com>2019-10-04 16:23:17 +0000
commit723591376e1900e9a26ce4781c59d5a3a6289a2c (patch)
treea571a76c2904b62e005abc0d66dc8ee0a9a999b4 /src/soc/intel/skylake
parent8595469093fb8ff3fee0a9c30661c3a872c05197 (diff)
downloadcoreboot-723591376e1900e9a26ce4781c59d5a3a6289a2c.tar.xz
soc/skl/vr_config: fix GT Loadline for KBL-U/GT3
According to the documentation[1], the Loadline in the unslased GT VR domain should be 2 mOhms for KBL-U (2 Core, GT3 + OPC). [1] page 109, 7th Generation Intel(R) Processor Families for U/Y Platforms and 8th Generation Intel(R) Processor Family for U Quad Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019. Document Number: 334661-006 Change-Id: I433036e76d456a725ab27cf57c9bc2fe01a7ace1 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35781 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/vr_config.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index fc48558f2e..de5ad2ca5c 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -286,7 +286,7 @@ static uint16_t get_sku_ac_dc_loadline(const int domain)
};
if (igd_id == PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22) {
- loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(6);
+ loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2);
loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6);
}