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authorMichael Niewöhner <foss@mniewoehner.de>2019-09-01 13:53:09 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-09-15 20:56:24 +0000
commita1ef94e822a0a2d1093e62d13ceb6dbeb19b22a1 (patch)
tree7defef16f2a0645c7778527b6a9ec13e2fb1b2d8 /src/soc/intel/skylake
parent5ea2e405dad22930db8f5e8dcf1a1fe383284919 (diff)
downloadcoreboot-a1ef94e822a0a2d1093e62d13ceb6dbeb19b22a1.tar.xz
soc/intel/skylake: add some FSP SATA params
This adds SATA parameters for SpinUp, HotPlug and TestMode to the Skylake FSP 2.0 interface. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I7ba67879b78c2cb0fd0b0ce832140b213edd5884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35186 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/chip.h5
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c5
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 1313dc15b9..fee14d8d7e 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -200,6 +200,8 @@ struct soc_intel_skylake_config {
u8 SataSalpSupport;
u8 SataPortsEnable[8];
u8 SataPortsDevSlp[8];
+ u8 SataPortsSpinUp[8];
+ u8 SataPortsHotPlug[8];
u8 SataSpeedLimit;
/* Audio related */
@@ -587,6 +589,9 @@ struct soc_intel_skylake_config {
/* Enable/Disable Sata power optimization */
u8 SataPwrOptEnable;
+
+ /* Enable/Disable Sata test mode */
+ u8 SataTestMode;
};
typedef struct soc_intel_skylake_config config_t;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index de869369a5..d1d7d6f50a 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -283,6 +283,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SataPortsEnable));
memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
sizeof(params->SataPortsDevSlp));
+ memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug,
+ sizeof(params->SataPortsHotPlug));
+ memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp,
+ sizeof(params->SataPortsSpinUp));
memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport,
sizeof(params->PcieRpClkReqSupport));
memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
@@ -369,6 +373,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
tconfig->PowerLimit4 = config->PowerLimit4;
+ tconfig->SataTestMode = config->SataTestMode;
/*
* To disable HECI, the Psf needs to be left unlocked
* by FSP till end of post sequence. Based on the devicetree