diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-08-19 11:03:59 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-08-29 07:18:49 +0000 |
| commit | 08a6fd309f9396fc7bdcbdc9608661da3a8c94a7 (patch) | |
| tree | 44d284b1378be4865ca9e4c219d11fddc1d01855 /src/soc/intel/skylake | |
| parent | 162aee9a5dd5c03c519b3a3542ba2eca0ee43c92 (diff) | |
| download | coreboot-08a6fd309f9396fc7bdcbdc9608661da3a8c94a7.tar.xz | |
intel/skylake: Fix RMT disable of saved training data
The RMT flag that was attempting to disable saved training to
force a full memory train was happening too late. In testing
I was actually hitting a case where FSP was training every time
but it was not because it was properly being told to.
This moves the check of the RMT flag from devicetree to happen
ealier, before it is actually consumed by romstage_common().
BUG=chrome-os-partner:40635
BRANCH=none
TEST=do both power off+on and warm resets to ensure that FSP
is doing a full memory train every time with RMT enabled.
Change-Id: Icf36e7b1ae20e08f6bc24bf832498d69b37dee92
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f3fa3846d51dec65f22f018acc8fb8c4d18688a7
Original-Change-Id: I2128b4a24bb8b2c8ddcb792c09b6fb0284d1fda4
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294177
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11417
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/pei_data.c | 14 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 7 |
2 files changed, 15 insertions, 6 deletions
diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c index 47198a7b9f..caee0784e0 100644 --- a/src/soc/intel/skylake/pei_data.c +++ b/src/soc/intel/skylake/pei_data.c @@ -18,11 +18,15 @@ * Foundation, Inc. */ +#include <chip.h> #include <console/console.h> #include <console/streams.h> +#include <device/device.h> +#include <device/pci_def.h> #include <stdlib.h> #include <stdint.h> #include <soc/iomap.h> +#include <soc/pci_devs.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/smm.h> @@ -34,6 +38,16 @@ static void ABI_X86 send_to_console(unsigned char b) void soc_fill_pei_data(struct pei_data *pei_data) { + const struct device *dev; + const struct soc_intel_skylake_config *config; + + /* Set the parameters for MemoryInit */ + dev = dev_find_slot(0, PCH_DEVFN_LPC); + config = dev->chip_info; + pei_data->pei_version = PEI_VERSION; pei_data->tx_byte = &send_to_console; + + /* Force a full memory train if RMT is enabled */ + pei_data->disable_saved_data = config->Rmt; } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index e9f0d4246b..91a496eb52 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -103,12 +103,7 @@ void soc_memory_init_params(struct romstage_params *params, upd->SataMode = config->SataMode; upd->EnableTraceHub = config->EnableTraceHub; upd->SaGv = config->SaGv; - - if (config->Rmt) { - upd->RMT = 1; - /* Force a full memory train if RMT is enabled */ - params->pei_data->disable_saved_data = 1; - } + upd->RMT = config->Rmt; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, |