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| author | Furquan Shaikh <furquan@chromium.org> | 2017-04-04 11:47:19 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-04-05 20:33:04 +0200 |
| commit | 340908aecf01093d35aaf0b71c55ed65c3ebbeac (patch) | |
| tree | 7d011dfbcc88e75c615b040a491ee1a979df844c /src/soc/intel/skylake | |
| parent | dd63f5978e44cdbf71047beb2e2b85c524ff3614 (diff) | |
| download | coreboot-340908aecf01093d35aaf0b71c55ed65c3ebbeac.tar.xz | |
soc/intel/lpss: Provide common LPSS clock config
Since there are multiple controllers in the LPSS and all use the same
frequency, provide a single Kconfig option for LPSS_CLOCK_MHZ.
BUG=b:35583330
Change-Id: I3c0cb62d56916e6e5f671fb5f40210f4cb33316f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 8ac7263c89..df8ae2bd2d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -109,10 +109,6 @@ config CPU_ADDR_BITS int default 36 -config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ - int - default 120 - config DCACHE_RAM_BASE hex "Base address of cache-as-RAM" default 0xfef00000 @@ -300,4 +296,8 @@ config NO_FADT_8042 help Choose this option if you want to disable 8042 Keyboard +config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ + int + default 120 + endif |