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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-14 19:30:46 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-04 09:40:21 +0000 |
| commit | b20aac072144e650dd5ba93bb4bfce1e061732e8 (patch) | |
| tree | 491b897f311f4057f898b0eac1f7ee146ca1c544 /src/soc/intel/skylake | |
| parent | 9e20e2f1587b4bba2db41a8279e070eac6ddd92b (diff) | |
| download | coreboot-b20aac072144e650dd5ba93bb4bfce1e061732e8.tar.xz | |
soc/intel/skl,acpi/acpigen: convert global CPPC package to local one
Move the global CPPC package \GCPC to the first logical core CP00 and
adapt the reference in the other cores. This is cleaner and avoids
confusion.
Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version
Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/acpi.c | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 637092be97..743b33f9ae 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -369,6 +369,19 @@ static void generate_p_state_entries(int core, int cores_per_package) acpigen_pop_len(); } +static void generate_cppc_entries(int core_id) +{ + /* Generate GCPC table in first logical core */ + if (core_id == 0) { + struct cppc_config cppc_config; + cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2); + acpigen_write_CPPC_package(&cppc_config); + } + + /* Write _CST entry for each logical core */ + acpigen_write_CPPC_method(); +} + void generate_cpu_entries(const struct device *device) { int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; @@ -377,16 +390,11 @@ void generate_cpu_entries(const struct device *device) int numcpus = totalcores/cores_per_package; config_t *config = config_of_soc(); int is_s0ix_enable = config->s0ix_enable; + const bool isst_supported = cpuid_eax(6) & CPUID_6_EAX_ISST; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); - if (cpuid_eax(6) & CPUID_6_EAX_ISST) { - struct cppc_config cppc_config; - cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); - acpigen_write_CPPC_package(&cppc_config); - } - for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { for (core_id = 0; core_id < cores_per_package; core_id++) { if (core_id > 0) { @@ -407,8 +415,8 @@ void generate_cpu_entries(const struct device *device) cores_per_package); } - if (cpuid_eax(6) & CPUID_6_EAX_ISST) - acpigen_write_CPPC_method(); + if (isst_supported) + generate_cppc_entries(core_id); acpigen_pop_len(); } |