soc/intel/skylake: Make use of common thermal code for SKL

This patch ensures skylake soc is using common thermal code
from intel common block.

TEST=Build and boot soraka

Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 2 insertions, 135 deletions

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index f36d5ca0f3..4def3b3927 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -69,6 +69,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
 	select SOC_INTEL_COMMON_BLOCK_UART
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
+	select SOC_INTEL_COMMON_BLOCK_THERMAL
 	select SOC_INTEL_COMMON_PCH_BASE
 	select SOC_INTEL_COMMON_NHLT
 	select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 913a9d9b5d..e2f5c1bb32 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -64,7 +64,6 @@ ramstage-y += sd.c
 ramstage-y += smmrelocate.c
 ramstage-y += spi.c
 ramstage-y += systemagent.c
-ramstage-y += thermal.c
 ramstage-y += uart.c
 ramstage-y += vr_config.c
 ramstage-y += xhci.c
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index da941dc643..6c105cea8c 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -585,9 +585,6 @@ struct soc_intel_skylake_config {
 	 */
 	u8 IslVrCmd;
 
-	/* PCH Trip Temperature */
-	u8 pch_trip_temp;
-
 	/* Enable/Disable Sata power optimization */
 	u8 SataPwrOptEnable;
 };
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 3c137c5871..8afaf4d344 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -26,6 +26,7 @@
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/p2sb.h>
 #include <intelblocks/pcr.h>
+#include <intelblocks/thermal.h>
 #include <reg_script.h>
 #include <spi-generic.h>
 #include <soc/me.h>
@@ -35,7 +36,6 @@
 #include <soc/pm.h>
 #include <soc/smbus.h>
 #include <soc/systemagent.h>
-#include <soc/thermal.h>
 #include <stdlib.h>
 #include <timer.h>
 
diff --git a/src/soc/intel/skylake/include/soc/thermal.h b/src/soc/intel/skylake/include/soc/thermal.h
deleted file mode 100644
index 31c47c6361..0000000000
--- a/src/soc/intel/skylake/include/soc/thermal.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_THERMAL_H_
-#define _SOC_THERMAL_H_
-
-#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c
-
-/* Enable thermal sensor power management */
-void pch_thermal_configuration(void);
-
-#endif
diff --git a/src/soc/intel/skylake/thermal.c b/src/soc/intel/skylake/thermal.c
deleted file mode 100644
index 006f3ae5cd..0000000000
--- a/src/soc/intel/skylake/thermal.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/mmio.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include <soc/thermal.h>
-
-#include "chip.h"
-
-#define MAX_TRIP_TEMP 205
-#define DEFAULT_TRIP_TEMP 50
-
-static void *pch_thermal_get_bar(struct device *dev)
-{
-	uintptr_t bar;
-
-	bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-	/*
-	 * Bits [31:12] are the base address as per EDS for Thermal Device,
-	 * Don't care about [11:0] bits
-	 */
-	return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
-}
-
-static void pch_thermal_set_bar(struct device *dev, uintptr_t tempbar)
-{
-	uint8_t pcireg;
-
-	/* Assign Resources to Thermal Device */
-	/* Clear BIT 1-2 of Command Register */
-	pcireg = pci_read_config8(dev, PCI_COMMAND);
-	pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-	pci_write_config8(dev, PCI_COMMAND, pcireg);
-
-	/* Program Temporary BAR for Thermal Device */
-	pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar);
-	pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0);
-
-	/* Enable Bus Master and MMIO Space */
-	pcireg = pci_read_config8(dev, PCI_COMMAND);
-	pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config8(dev, PCI_COMMAND, pcireg);
-}
-
-/* PCH Low Temp Threshold (LTT) */
-static uint16_t pch_get_ltt_value(struct device *dev)
-{
-	struct soc_intel_skylake_config *config;
-	uint16_t ltt_value;
-	uint16_t trip_temp = DEFAULT_TRIP_TEMP;
-
-	config = config_of(dev);
-
-	if (config->pch_trip_temp)
-		trip_temp = config->pch_trip_temp;
-
-	if (trip_temp > MAX_TRIP_TEMP)
-		die("Input PCH temp trip is higher than allowed range!");
-
-	/* Trip Point Temp = (LTT / 2 - 50 degree C) */
-	ltt_value = (trip_temp + 50) * 2;
-
-	return ltt_value;
-}
-
-/* Enable thermal sensor power management */
-void pch_thermal_configuration(void)
-{
-	uint16_t reg16;
-	struct device *dev = PCH_DEV_THERMAL;
-	if (!dev) {
-		printk(BIOS_ERR, "PCH_DEV_THERMAL device not found!\n");
-		return;
-	}
-	void *thermalbar = pch_thermal_get_bar(dev);
-
-	/* Use default pre-ram bar */
-	if (!thermalbar) {
-		pch_thermal_set_bar(dev, THERMAL_BASE_ADDRESS);
-		thermalbar = (void *)THERMAL_BASE_ADDRESS;
-	}
-
-	/* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */
-	reg16 = read16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT);
-	reg16 &= ~0x1ff;
-	/* Low Temp Threshold (LTT) */
-	reg16 |= pch_get_ltt_value(dev);
-	write16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT, reg16);
-}