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| author | Furquan Shaikh <furquan@chromium.org> | 2017-10-09 23:55:51 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-10 14:43:54 +0000 |
| commit | d6c0af6c549b9e4a6f3a6ad0e9ce6a37087c6e9a (patch) | |
| tree | af6dad20c3484aae2efe0e177a9defe632d326b3 /src/soc/intel/skylake | |
| parent | 5547c371c11f270c73ad822d4448ff8e1a3868d6 (diff) | |
| download | coreboot-d6c0af6c549b9e4a6f3a6ad0e9ce6a37087c6e9a.tar.xz | |
soc/intel/skylake: Fix broken suspend/resume for deep S3
Change d3476809 (soc/intel/skylake: Add support in SKL for PMC common
code) changed the logic for obtaining previous sleep state by
unconditionally checking for PWR_FLR and SUS_PWR_FLR. In case of deep
S3, SUS_PWR_FLR is set in gen_pmcon_b (just like resume from deep
S5/G3) and hence the check for power failure should be done only when
WAK_STS bit is not set. This is necessary to differentiate wakes from
deep S3 and G3.
This change restores the original logic by performing power failure
check only in cases where WAK_STS bit is not set.
BUG=b:67617726
TEST=Verified following:
1. When WAK_STS bit is not set and SUS_PWR_FLR is set, coreboot
correctly identifies that the system prev sleep state was S5.
2. When WAK_STS bit is set and SUS_PWR_FLR is set, coreboot correctly
identifies that the system prev sleep state was S3.
Change-Id: Ic97bbc9911ba34aa21f4728c77fc20c5bb08f6f9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
| -rw-r--r-- | src/soc/intel/skylake/romstage/power_state.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c index 78650fa590..3eae936337 100644 --- a/src/soc/intel/skylake/romstage/power_state.c +++ b/src/soc/intel/skylake/romstage/power_state.c @@ -44,7 +44,8 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, * S5 because the PCH does not set the WAK_STS bit when waking * from a true G3 state. */ - if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) + if (!(ps->pm1_sts & WAK_STS) && + (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))) prev_sleep_state = ACPI_S5; /* |