intel/skylake: ACPI: Clean up formatting in and fix ASL code

Clean up the formatting in various ASL files and remove
unused and/or incorrect field definitions.

Add back the methods to set the USB power in S3 field
in NVS as it is called by the chromium kernel at boot and
is currently complaining that the method is not found.

BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I9726fb337bf53fa7dce72c5f30524b58abb4cab6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3a47eeba2792c3abed07be175034c709dbf60879
Original-Change-Id: I8e8388c9b834fd060990f8e069929ba829e29ab6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295952
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11539
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 216 insertions, 296 deletions

diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index 0208198a06..31711d1d3b 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -68,7 +68,18 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
+}
 
+/* Set flag to enable USB charging in S3 */
+Method (S3UE)
+{
+	Store (One, \S3U0)
+}
+
+/* Set flag to disable USB charging in S3 */
+Method (S3UD)
+{
+	Store (Zero, \S3U0)
 }
 
 /* Set flag to enable USB charging in S5 */
diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl
index 877be991b4..c841311cfb 100644
--- a/src/soc/intel/skylake/acpi/lpc.asl
+++ b/src/soc/intel/skylake/acpi/lpc.asl
@@ -19,33 +19,16 @@
  * Foundation, Inc.
  */
 
-
-// Intel LPC Bus Device  - 0:1f.0
-
 Device (LPCB)
 {
 	Name (_ADR, 0x001f0000)
+	Name (_DDN, "LPC Bus Device")
 
-	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
-	Field (LPC0, AnyAcc, NoLock, Preserve)
-	{
-		Offset (0x02),
-		PDID,	16,	// Device ID
-		Offset (0x40),
-		PMBS,	16,	// PMBASE
-		Offset (0x48),
-		GPBS,	16,	// GPIOBASE
-
-
-		Offset (0x80),	// IO Decode Ranges
-		IOD0,	8,
-		IOD1,	8,
-	}
-
-	Device (DMAC)	// DMA Controller
+	Device (DMAC)
 	{
-		Name (_HID, EISAID("PNP0200"))
-		Name (_CRS, ResourceTemplate()
+		Name (_HID, EISAID ("PNP0200"))
+		Name (_DDN, "DMA Controller")
+		Name (_CRS, ResourceTemplate ()
 		{
 			IO (Decode16, 0x00, 0x00, 0x01, 0x20)
 			IO (Decode16, 0x81, 0x81, 0x01, 0x11)
@@ -55,40 +38,34 @@ Device (LPCB)
 		})
 	}
 
-	Device (FWH)	// Firmware Hub
+	Device (FWH)
 	{
-		Name (_HID, EISAID("INT0800"))
-		Name (_CRS, ResourceTemplate()
+		Name (_HID, EISAID ("INT0800"))
+		Name (_DDN, "Firmware Hub")
+		Name (_CRS, ResourceTemplate ()
 		{
-			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+			Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
 		})
 	}
 
 	Device (HPET)
 	{
-		Name (_HID, EISAID("PNP0103"))
-		Name (BUF0, ResourceTemplate()
+		Name (_HID, EISAID ("PNP0103"))
+		Name (_DDN, "High Precision Event Timer")
+		Name (_CRS, ResourceTemplate ()
 		{
-			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
+			Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
 		})
-
-		Method (_STA, 0)	// Device Status
+		Method (_STA, 0)
 		{
 			Return (0xf)
 		}
-		Method (_CRS, 0, Serialized) // Current resources
-		{
-			CreateDWordField (BUF0, ^FED0._BAS, HPT0)
-			/* TODO: Base address configured need to pass as GNVS */
-			Store(HPET_BASE_ADDRESS, HPT0)
-
-			Return(BUF0)
-		}
 	}
 
-	Device(PIC)	// 8259 Interrupt Controller
+	Device (PIC)
 	{
-		Name (_HID,EISAID("PNP0000"))
+		Name (_HID, EISAID ("PNP0000"))
+		Name (_DDN, "8259 Interrupt Controller")
 		Name (_CRS, ResourceTemplate()
 		{
 			IO (Decode16, 0x20, 0x20, 0x01, 0x02)
@@ -112,22 +89,23 @@ Device (LPCB)
 		})
 	}
 
-	Device(MATH)	// FPU
+	Device (MATH)
 	{
-		Name (_HID, EISAID("PNP0C04"))
-		Name (_CRS, ResourceTemplate()
+		Name (_HID, EISAID ("PNP0C04"))
+		Name (_DDN, "Floating Point Unit")
+		Name (_CRS, ResourceTemplate ()
 		{
 			IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
-			IRQNoFlags() { 13 }
+			IRQNoFlags () { 13 }
 		})
 	}
 
-	Device(LDRC)	// LPC device: Resource consumption
+	Device (LDRC)
 	{
-		Name (_HID, EISAID("PNP0C02"))
+		Name (_HID, EISAID ("PNP0C02"))
 		Name (_UID, 2)
-
-		Name (RBUF, ResourceTemplate()
+		Name (_DDN, "Legacy Device Resources")
+		Name (_CRS, ResourceTemplate ()
 		{
 			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
 			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
@@ -141,30 +119,27 @@ Device (LPCB)
 			IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
 			    0x1, 0xff)
 		})
-
-		Method (_CRS, 0, NotSerialized)
-		{
-			Return (RBUF)
-		}
 	}
 
-	Device (RTC)	// Real Time Clock
+	Device (RTC)
 	{
-		Name (_HID, EISAID("PNP0B00"))
-		Name (_CRS, ResourceTemplate()
+		Name (_HID, EISAID ("PNP0B00"))
+		Name (_DDN, "Real Time Clock")
+		Name (_CRS, ResourceTemplate ()
 		{
 			IO (Decode16, 0x70, 0x70, 1, 8)
-			//IRQNoFlags() { 8 }
 		})
 	}
 
-	Device (TIMR)	// Intel 8254 timer
+	Device (TIMR)
 	{
-		Name (_HID, EISAID("PNP0100"))
-		Name (_CRS, ResourceTemplate() {
+		Name (_HID, EISAID ("PNP0100"))
+		Name (_DDN, "8254 Timer")
+		Name (_CRS, ResourceTemplate ()
+		{
 			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
 			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
-			IRQNoFlags() {0}
+			IRQNoFlags () {0}
 		})
 	}
 
diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl
index c43e42dbb6..3bf5f3e442 100644
--- a/src/soc/intel/skylake/acpi/pci_irqs.asl
+++ b/src/soc/intel/skylake/acpi/pci_irqs.asl
@@ -19,125 +19,121 @@
  * Foundation, Inc.
  */
 
-Method(_PRT)
+Name (PICP, Package () {
+	/* D31: cAVS, SMBus, GbE, Nothpeak */
+	Package () { 0x001FFFFF, 0, 0, 16 },
+	Package () { 0x001FFFFF, 1, 0, 17 },
+	Package () { 0x001FFFFF, 2, 0, 18 },
+	Package () { 0x001FFFFF, 3, 0, 19 },
+	/* D30: SerialIo and SCS */
+	Package () { 0x001EFFFF, 0, 0, 20 },
+	Package () { 0x001EFFFF, 1, 0, 21 },
+	Package () { 0x001EFFFF, 2, 0, 22 },
+	Package () { 0x001EFFFF, 3, 0, 23 },
+	/* D29: PCI Express Port 9-16 */
+	Package () { 0x001DFFFF, 0, 0, 16 },
+	Package () { 0x001DFFFF, 1, 0, 17 },
+	Package () { 0x001DFFFF, 2, 0, 18 },
+	Package () { 0x001DFFFF, 3, 0, 19 },
+	/* D28: PCI Express Port 1-8 */
+	Package () { 0x001CFFFF, 0, 0, 16 },
+	Package () { 0x001CFFFF, 1, 0, 17 },
+	Package () { 0x001CFFFF, 2, 0, 18 },
+	Package () { 0x001CFFFF, 3, 0, 19 },
+	/* D27: PCI Express Port 17-20 */
+	Package () { 0x001BFFFF, 0, 0, 16 },
+	Package () { 0x001BFFFF, 1, 0, 17 },
+	Package () { 0x001BFFFF, 2, 0, 18 },
+	Package () { 0x001BFFFF, 3, 0, 19 },
+	/* D25: SerialIo */
+	Package () { 0x0019FFFF, 0, 0, 32 },
+	Package () { 0x0019FFFF, 1, 0, 33 },
+	Package () { 0x0019FFFF, 2, 0, 34 },
+	/* D22: CSME (HECI, IDE-R, KT redirection */
+	Package () { 0x0016FFFF, 0, 0, 16 },
+	Package () { 0x0016FFFF, 1, 0, 17 },
+	Package () { 0x0016FFFF, 2, 0, 18 },
+	Package () { 0x0016FFFF, 3, 0, 19 },
+	/* D21: SerialIo */
+	Package () { 0x0015FFFF, 0, 0, 16 },
+	Package () { 0x0015FFFF, 1, 0, 17 },
+	Package () { 0x0015FFFF, 2, 0, 18 },
+	Package () { 0x0015FFFF, 3, 0, 19 },
+	/* D20: xHCI, OTG, Thermal, Camera */
+	Package () { 0x0014FFFF, 0, 0, 16 },
+	Package () { 0x0014FFFF, 1, 0, 17 },
+	Package () { 0x0014FFFF, 2, 0, 18 },
+	Package () { 0x0014FFFF, 3, 0, 19 },
+	/* D19: Integrated Sensor Hub */
+	Package () { 0x0013FFFF, 0, 0, 20 },
+	/* P.E.G. Root Port D1F0 */
+	Package () { 0x0001FFFF, 0, 0, 16 },
+	Package () { 0x0001FFFF, 1, 0, 17 },
+	Package () { 0x0001FFFF, 2, 0, 18 },
+	Package () { 0x0001FFFF, 3, 0, 19 },
+	/* SA IGFX Device */
+	Package () { 0x0002FFFF, 0, 0, 16 },
+	/* SA Thermal Device */
+	Package () { 0x0004FFFF, 0, 0, 16 },
+	/* SA SkyCam Device */
+	Package () { 0x0005FFFF, 0, 0, 16 },
+	/* SA GMM Device */
+	Package () { 0x0008FFFF, 0, 0, 16 },
+})
+
+Name (PICN, Package () {
+	/* D31: cAVS, SMBus, GbE, Nothpeak */
+	Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D29: PCI Express Port 9-16 */
+	Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D28: PCI Express Port 1-8 */
+	Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D27: PCI Express Port 17-20 */
+	Package () { 0x001BFFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x001BFFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x001BFFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x001BFFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D23 */
+	Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* D22: CSME (HECI, IDE-R, KT redirection */
+	Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* D20: xHCI, OTG, Thermal, Camera */
+	Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* P.E.G. Root Port D1F0 */
+	Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },
+	Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },
+	Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },
+	/* SA IGFX Device */
+	Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* SA Thermal Device */
+	Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* SA Skycam Device */
+	Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },
+	/* SA GMM Device */
+	Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },
+})
+
+Method (_PRT)
 {
 	If (PICM) {
-		Return (Package() {
-		/* PCI Bridge */
-		/* D31: cAVS, SMBus, GbE, Nothpeak */
-			Package(){0x001FFFFF, 0, 0, 16 },
-			Package(){0x001FFFFF, 1, 0, 17 },
-			Package(){0x001FFFFF, 2, 0, 18 },
-			Package(){0x001FFFFF, 3, 0, 19 },
-		/* D30: SerialIo and SCS */
-			Package(){0x001EFFFF, 0, 0, 20 },
-			Package(){0x001EFFFF, 1, 0, 21 },
-			Package(){0x001EFFFF, 2, 0, 22 },
-			Package(){0x001EFFFF, 3, 0, 23 },
-		/* D29: PCI Express Port 9-16 */
-			Package(){0x001DFFFF, 0, 0, 16 },
-			Package(){0x001DFFFF, 1, 0, 17 },
-			Package(){0x001DFFFF, 2, 0, 18 },
-			Package(){0x001DFFFF, 3, 0, 19 },
-		/* D28: PCI Express Port 1-8 */
-			Package(){0x001CFFFF, 0, 0, 16 },
-			Package(){0x001CFFFF, 1, 0, 17 },
-			Package(){0x001CFFFF, 2, 0, 18 },
-			Package(){0x001CFFFF, 3, 0, 19 },
-		/* D27: PCI Express Port 17-20 */
-			Package(){0x001BFFFF, 0, 0, 16 },
-			Package(){0x001BFFFF, 1, 0, 17 },
-			Package(){0x001BFFFF, 2, 0, 18 },
-			Package(){0x001BFFFF, 3, 0, 19 },
-		/* D25: SerialIo */
-			Package(){0x0019FFFF, 0, 0, 32 },
-			Package(){0x0019FFFF, 1, 0, 33 },
-			Package(){0x0019FFFF, 2, 0, 34 },
-		/* D22: CSME (HECI, IDE-R, Keyboard and Text redirection */
-			Package(){0x0016FFFF, 0, 0, 16 },
-			Package(){0x0016FFFF, 1, 0, 17 },
-			Package(){0x0016FFFF, 2, 0, 18 },
-			Package(){0x0016FFFF, 3, 0, 19 },
-		/* D21: SerialIo */
-			Package(){0x0015FFFF, 0, 0, 16 },
-			Package(){0x0015FFFF, 1, 0, 17 },
-			Package(){0x0015FFFF, 2, 0, 18 },
-			Package(){0x0015FFFF, 3, 0, 19 },
-		/* D20: xHCI, OTG,
-		 * Thermal Subsystem, Camera IO Host Controller
-		 */
-			Package(){0x0014FFFF, 0, 0, 16 },
-			Package(){0x0014FFFF, 1, 0, 17 },
-			Package(){0x0014FFFF, 2, 0, 18 },
-			Package(){0x0014FFFF, 3, 0, 19 },
-		/* D19: Integrated Sensor Hub */
-			Package(){0x0013FFFF, 0, 0, 20 },
-
-		/* Host Bridge */
-		/* P.E.G. Root Port D1F0 */
-			Package(){0x0001FFFF, 0, 0, 16 },
-			Package(){0x0001FFFF, 1, 0, 17 },
-			Package(){0x0001FFFF, 2, 0, 18 },
-			Package(){0x0001FFFF, 3, 0, 19 },
-		/* P.E.G. Root Port D1F1 */
-		/* P.E.G. Root Port D1F2 */
-		/* SA IGFX Device */
-			Package(){0x0002FFFF, 0, 0, 16 },
-		/* SA Thermal Device */
-			Package(){0x0004FFFF, 0, 0, 16 },
-		/* SA SkyCam Device */
-			Package(){0x0005FFFF, 0, 0, 16 },
-		/* SA GMM Device */
-			Package(){0x0008FFFF, 0, 0, 16 },
-		})
+		Return (^PICP)
 	} Else {
-		Return (Package() {
-		/* D31 */
-		Package() { 0x001fffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x001fffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x001fffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x001fffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D29 */
-		Package() { 0x001dffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x001dffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x001dffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x001dffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D28 */
-		Package() { 0x001cffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x001cffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x001cffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x001cffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D27 */
-		Package() { 0x001bffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x001bffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x001bffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x001bffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D23 */
-		Package() { 0x0017ffff, 0, \_SB.PCI0.LNKA, 0 },
-		/* D22 */
-		Package() { 0x0016ffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x0016ffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x0016ffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x0016ffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* D20 */
-		Package() { 0x0014ffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x0014ffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x0014ffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x0014ffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* Host bridge */
-		Package() { 0x0001ffff, 0, \_SB.PCI0.LNKA, 0 },
-		Package() { 0x0001ffff, 1, \_SB.PCI0.LNKB, 0 },
-		Package() { 0x0001ffff, 2, \_SB.PCI0.LNKC, 0 },
-		Package() { 0x0001ffff, 3, \_SB.PCI0.LNKD, 0 },
-		/* SA IGFX Device */
-		Package() { 0x0002ffff, 0, \_SB.PCI0.LNKA, 0 },
-		/* SA Thermal Device */
-		Package() { 0x0004ffff, 0, \_SB.PCI0.LNKA, 0 },
-		/* SA Skycam Device */
-		Package() { 0x0005ffff, 0, \_SB.PCI0.LNKA, 0 },
-		/* SA GMM Device */
-		Package() { 0x0008ffff, 0, \_SB.PCI0.LNKA, 0 },
-		})
+		Return (^PICN)
 	}
 }
-
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index b8fec94e9e..9c9fc1749d 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Google Inc.
  * Copyright (C) 2015 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -24,121 +24,73 @@
 #define BASE_32GB	0x800000000
 #define SIZE_16GB	0x400000000
 
-Name (_HID, EISAID ("PNP0A08"))	// PCIe
-Name (_CID, EISAID ("PNP0A03"))	// PCI
+Name (_HID, EISAID ("PNP0A08"))	/* PCIe */
+Name (_CID, EISAID ("PNP0A03"))	/* PCI */
 
 Name (_ADR, 0)
 Name (_BBN, 0)
 
 Device (MCHC)
 {
-	Name (_ADR, 0x00000000)	// 0:0.0
+	Name (_ADR, 0x00000000)
 
 	OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
 	Field (MCHP, DWordAcc, NoLock, Preserve)
 	{
-		Offset(0x40),	// EPBAR (0:0:0:40)
-		EPEN, 1,		// Enable
-			, 11,
-		EPBR, 20,		// EPBAR [31:12]
-
-		Offset(0x48),	// MCHBAR (0:0:0:48)
-		MHEN, 1,		// Enable
-			, 14,
-		MHBR, 17,	// MCHBAR [31:15]
-
-		Offset(0x54),	// DEVEN (0:0:0:54)
-		D0EN, 1,		// DEV0 Enable
-		D1F2, 1,		// DEV1 FUN2 Enable
-		D1F1, 1,		// DEV1 FUN1 Enable
-		D1F0, 1,		// DEV1 FUN0 Enable
-
-		Offset(0x60),	// PCIEXBAR (0:0:0:60)
-		PXEN, 1,		// Enable
-		PXSZ, 2,		// PCI Express Size
-			, 23,
-		PXBR, 6,		// PCI Express BAR [31:26]
-
-		Offset(0x68),	// DMIBAR (0:0:0:68)
-		DIEN, 1,		// Enable
-			, 11,
-		DIBR, 20,		// DMIBAR [31:12]
-
-		Offset (0x70),	// ME Base Address
+		Offset(0x40),	/* EPBAR (0:0:0:40) */
+		EPEN, 1,	/* Enable */
+		, 11,
+		EPBR, 20,	/* EPBAR [31:12] */
+
+		Offset(0x48),	/* MCHBAR (0:0:0:48) */
+		MHEN, 1,	/* Enable */
+		, 14,
+		MHBR, 17,	/* MCHBAR [31:15] */
+
+		Offset(0x60),	/* PCIEXBAR (0:0:0:60) */
+		PXEN, 1,	/* Enable */
+		PXSZ, 2,	/* PCI Express Size */
+		, 23,
+		PXBR, 6,	/* PCI Express BAR [31:26] */
+
+		Offset(0x68),	/* DMIBAR (0:0:0:68) */
+		DIEN, 1,	/* Enable */
+		, 11,
+		DIBR, 20,	/* DMIBAR [31:12] */
+
+		Offset (0x70),	/* ME Base Address */
 		MEBA, 64,
 
-		Offset(0x80),	// PAM0 Register (0:0:0:80)
-		PMLK, 1,		// PAM Lock bit.
-			, 3,
-		PM0H, 2,		// PAM 0, High Nibble
-			, 2,
-
-		Offset(0x81),	// PAM1 Register (0:0:0:81)
-		PM1L, 2,		// PAM1, Low  Nibble
-			, 2,
-		PM1H, 2,		// PAM1, High Nibble
-			, 2,
-
-		Offset(0x82),	// PAM2 Register (0:0:0:82)
-		PM2L, 2,		// PAM2, Low  Nibble
-			, 2,
-		PM2H, 2,		// PAM2, High Nibble
-			, 2,
-
-		Offset(0x83),	// PAM3 Register (0:0:0:83)
-		PM3L, 2,		// PAM3, Low  Nibble
-			, 2,
-		PM3H, 2,		// PAM3, High Nibble
-			, 2,
-
-		Offset(0x84),	// PAM4 Register (0:0:0:84)
-		PM4L, 2,		// PAM4, Low  Nibble
-			, 2,
-		PM4H, 2,		// PAM4, High Nibble
-			, 2,
-
-		Offset(0x85),	// PAM5 Register (0:0:0:85)
-		PM5L, 2,		// PAM5, Low  Nibble
-			, 2,
-		PM5H, 2,		// PAM5, High Nibble
-			, 2,
-
-		Offset(0x86),	// PAM6 Register (0:0:0:86)
-		PM6L, 2,		// PAM6, Low  Nibble
-			, 2,
-		PM6H, 2,		// PAM6, High Nibble
-			, 2,
-
-		Offset (0xa0),	// Top of Used Memory
+		Offset (0xa0),	/* Top of Used Memory */
 		TOM, 64,
 
-		Offset (0xa8),	// Top of Upper Used Memory
+		Offset (0xa8),	/* Top of Upper Used Memory */
 		TUUD, 64,
 
-		Offset (0xbc),	// Top of Low Used Memory
+		Offset (0xbc),	/* Top of Low Used Memory */
 		TLUD, 32,
 	}
 }
 
-// Current Resource Settings
-
 Method (_CRS, 0, Serialized)
 {
-	Name (MCRS, ResourceTemplate()
+	Name (MCRS, ResourceTemplate ()
 	{
 		/* Bus Numbers */
 		WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
 				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
 
 		/* IO Region 0 */
-		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				EntireRange,
 				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
 
 		/* PCI Config Space */
 		Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
 
 		/* IO Region 1 */
-		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				EntireRange,
 				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
 
 		/* VGA memory (0xa0000-0xbffff) */
@@ -278,13 +230,10 @@ Method (_CRS, 0, Serialized)
 
 	Store (^MCHC.TUUD, Local0)
 
-	If (LLessEqual (Local0, BASE_32GB))
-	{
+	If (LLessEqual (Local0, BASE_32GB)) {
 		Store (BASE_32GB, MMIN)
 		Store (SIZE_16GB, MLEN)
-	}
-	else
-	{
+	} Else {
 		Store (0, MMIN)
 		Store (0, MLEN)
 	}
@@ -300,50 +249,45 @@ Name (PC_L, 0) /* to store PCIe BAR Length */
 Name (DM_B, 0) /* to store DMI BAR */
 
 /* Get MCH BAR */
-Method (GMHB,0,Serialized)
+Method (GMHB, 0, Serialized)
 {
-	if (LEqual (MH_B,0))
-	{
+	If (LEqual (MH_B, 0)) {
 		ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B)
 	}
 	Return (MH_B)
 }
 
 /* Get EP BAR */
-Method (GEPB,0,Serialized)
+Method (GEPB, 0, Serialized)
 {
-	if (LEqual (EP_B,0))
-	{
+	If (LEqual (EP_B, 0)) {
 		ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B)
 	}
 	Return (EP_B)
 }
 
 /* Get PCIe BAR */
-Method (GPCB,0,Serialized)
+Method (GPCB, 0, Serialized)
 {
-	if (LEqual (PC_B,0))
-	{
+	If (LEqual (PC_B, 0)) {
 		ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B)
 	}
 	Return (PC_B)
 }
 
 /* Get PCIe Length */
-Method (GPCL,0,Serialized)
+Method (GPCL, 0, Serialized)
 {
-	if (LEqual (PC_L,0))
-	{
+	If (LEqual (PC_L, 0)) {
 		ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L)
 	}
 	Return (PC_L)
 }
 
 /* Get DMI BAR */
-Method (GDMB,0,Serialized)
+Method (GDMB, 0, Serialized)
 {
-	if (LEqual (DM_B,0))
-	{
+	If (LEqual (DM_B, 0)) {
 		ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B)
 	}
 	Return (DM_B)
@@ -352,10 +296,10 @@ Method (GDMB,0,Serialized)
 /* PCI Device Resource Consumption */
 Device (PDRC)
 {
-	Name (_HID, EISAID("PNP0C02"))
+	Name (_HID, EISAID ("PNP0C02"))
 	Name (_UID, 1)
 
-	Name (BUF0,ResourceTemplate()
+	Name (BUF0, ResourceTemplate ()
 	{
 		/* MCH BAR _BAS will be updated in _CRS below according to
 		 * B0:D0:F0:Reg.48h
@@ -398,8 +342,8 @@ Device (PDRC)
 		/* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
 		Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
 
-		/* Reserve HPET address decode range */
-		Memory32Fixed (ReadWrite, 0, 0, HPET)
+		/* HPET address decode range */
+		Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
 
 		/* Debug Base Address
 		 * Base Address for ACPI debug output memory buffer
@@ -407,28 +351,22 @@ Device (PDRC)
 		Memory32Fixed (ReadWrite, 0, 0, DBAD)
 	})
 
-	// Current Resource Settings
 	Method (_CRS, 0, Serialized)
 	{
 		CreateDwordField (BUF0, ^MCHB._BAS, MBR0)
-		Store (\_SB.PCI0.GMHB(), MBR0)
+		Store (\_SB.PCI0.GMHB (), MBR0)
 
 		CreateDwordField (BUF0, ^DMIB._BAS, DBR0)
-		Store (\_SB.PCI0.GDMB(), DBR0)
+		Store (\_SB.PCI0.GDMB (), DBR0)
 
 		CreateDwordField (BUF0, ^EGPB._BAS, EBR0)
-		Store (\_SB.PCI0.GEPB(), EBR0)
+		Store (\_SB.PCI0.GEPB (), EBR0)
 
 		CreateDwordField (BUF0, ^PCIX._BAS, XBR0)
-		Store (\_SB.PCI0.GPCB(), XBR0)
+		Store (\_SB.PCI0.GPCB (), XBR0)
 
 		CreateDwordField (BUF0, ^PCIX._LEN, XSZ0)
-		Store (\_SB.PCI0.GPCL(),  XSZ0)
-
-		CreateDwordField (BUF0, ^HPET._BAS, HBAS)
-		CreateDwordField (BUF0, ^HPET._LEN, HLEN)
-		Store (0xfed00000, HBAS)
-		Store (0x400, HLEN)
+		Store (\_SB.PCI0.GPCL (), XSZ0)
 
 		Return (BUF0)
 	}