summaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake
diff options
context:
space:
mode:
authorFurquan Shaikh <furquan@chromium.org>2017-05-25 00:14:35 -0700
committerFurquan Shaikh <furquan@google.com>2017-05-27 05:29:32 +0200
commit1cf7f86d92e7ea4a49d06e4aebf7213b259933fa (patch)
tree08a0e31568df169e01b428ab5a3bf2c6a8d789ad /src/soc/intel/skylake
parentb858157dbaf2914439fcca434a72a16ad551e6e3 (diff)
downloadcoreboot-1cf7f86d92e7ea4a49d06e4aebf7213b259933fa.tar.xz
soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions
This is required to add wake sources for PCIE PME events. BUG=b:37088992 Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/include/soc/pci_devs.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index f51691c80b..91e612d417 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -111,12 +111,18 @@
#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3)
#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4)
#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5)
+#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6)
+#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7)
#define PCH_DEV_SLOT_PCIE_1 0x1d
#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0)
#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1)
#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2)
#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3)
+#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0)
+#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1)
+#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2)
+#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3)
#define PCH_DEV_SLOT_STORAGE 0x1e
#define PCH_DEVFN_UART0 _PCH_DEVFN(STORAGE, 0)