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authorElyes HAOUAS <ehaouas@noos.fr>2019-03-06 13:06:54 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-03-07 17:17:12 +0000
commit2d4e836f119e2b7c953e11a941690058e9f33095 (patch)
tree9f638f22eb8d4f231375d91cdecc4b283e62c63b /src/soc/intel/skylake
parentae546422edf73d47b60a0d3caa88c48024d2e8a9 (diff)
downloadcoreboot-2d4e836f119e2b7c953e11a941690058e9f33095.tar.xz
src: Drop unused include <timestamp.h>
Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/skylake')
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index cf4bffccd6..e147f0c0aa 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -37,7 +37,6 @@
#include <stage_cache.h>
#include <stddef.h>
#include <stdint.h>
-#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
/* SOC initialization before RAM is enabled */